github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-05-02 13:44:00 +00:00
Code Issues Projects Releases Wiki Activity

DM: increase vioapic pin count

Browse Source 
Current only 8 vioapic pins for pci irq (total 24 with 16 reserved),
which easily leads virtual GSI sharing with more and more passthrough
devices. This patch doulbes vioapic pin count and adds reboot hooks to
allocate from same pin after each reboot.

Signed-off-by: Edwin Zhai <edwin.zhai@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Edwin Zhai 2018-05-15 09:32:29 +08:00 committed by lijinxia
parent e1bb372763
commit 30549a59c7
6 changed files with 25 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
devicemodel/core/main.c
View File

@ -501,6 +501,7 @@ vrtc_fail:
ioc_deinit(ctx);
atkbdc_deinit(ctx);
pci_irq_deinit(ctx);
ioapic_deinit();
return -1;
}
@ -514,6 +515,7 @@ vm_deinit_vdevs(struct vmctx *ctx)
ioc_deinit(ctx);
atkbdc_deinit(ctx);
pci_irq_deinit(ctx);
ioapic_deinit();
}
static void

7
devicemodel/core/vmmapi.c
View File

@ -618,13 +618,6 @@ vm_isa_pulse_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq)
return vm_isa_irq(ctx, atpic_irq, ioapic_irq, IC_PULSE_IRQLINE);
}
int
vm_ioapic_pincount(struct vmctx *ctx, int *pincount)
{
*pincount = 24;
return 0;
}
int
vm_assign_ptdev(struct vmctx *ctx, int bus, int slot, int func)
{

27
devicemodel/hw/platform/ioapic.c
View File

@ -36,6 +36,9 @@
#include "pci_core.h"
#include "lpc.h"
/* 16 IRQs reserved for kdb/mouse, COM1/2, RTC... */
#define LEGACY_IRQ_NUM 16
/*
* Assign PCI INTx interrupts to I/O APIC pins in a round-robin
* fashion. Note that we have no idea what the HPET is using, but the
@ -46,29 +49,27 @@
* PCI devices.
*/
static int pci_pins;
static int last_pin;
void
ioapic_init(struct vmctx *ctx)
{
if (vm_ioapic_pincount(ctx, &pci_pins) < 0) {
pci_pins = 0;
return;
last_pin = 0;
/* Ignore the first 16 pins for legacy IRQ. */
pci_pins = VIOAPIC_RTE_NUM - LEGACY_IRQ_NUM;
}
/* Ignore the first 16 pins. */
if (pci_pins <= 16) {
pci_pins = 0;
return;
}
pci_pins -= 16;
void ioapic_deinit(void)
{
last_pin = 0;
}
int
ioapic_pci_alloc_irq(struct pci_vdev *dev)
{
static int last_pin;
/* No support of vGSI sharing */
assert(last_pin < pci_pins);
if (pci_pins == 0)
return -1;
return (16 + (last_pin++ % pci_pins));
return (LEGACY_IRQ_NUM + (last_pin++ % pci_pins));
}

1
devicemodel/include/ioapic.h
View File

@ -36,6 +36,7 @@ struct pci_vdev;
* Allocate a PCI IRQ from the I/O APIC.
*/
void ioapic_init(struct vmctx *ctx);
void ioapic_deinit(void);
int ioapic_pci_alloc_irq(struct pci_vdev *pi);
#endif

7
devicemodel/include/public/acrn_common.h
View File

@ -82,6 +82,13 @@
#define REQUEST_READ 0
#define REQUEST_WRITE 1
/* IOAPIC device model info */
#define VIOAPIC_RTE_NUM 48 /* vioapic pins */
#if VIOAPIC_RTE_NUM < 24
#error "VIOAPIC_RTE_NUM must be larger than 23"
#endif
/* Generic VM flags from guest OS */
#define SECURE_WORLD_ENABLED (1UL<<0) /* Whether secure world is enabled */

1
devicemodel/include/vmmapi.h
View File

@ -140,7 +140,6 @@ int vm_apicid2vcpu(struct vmctx *ctx, int apicid);
int vm_lapic_msi(struct vmctx *ctx, uint64_t addr, uint64_t msg);
int vm_ioapic_assert_irq(struct vmctx *ctx, int irq);
int vm_ioapic_deassert_irq(struct vmctx *ctx, int irq);
int vm_ioapic_pincount(struct vmctx *ctx, int *pincount);
int vm_isa_assert_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq);
int vm_isa_deassert_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq);
int vm_isa_pulse_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq);