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dm: confiure msix bar for hv-land ivshmem devices

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This patch configures MSIX entry table bar for hv-land ivhsmem devices.

Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yonghua Huang 2020-10-22 17:07:42 +08:00 committed by wenlingz
parent 9b4ba19753
commit 30bbfa0d26
1 changed files with 10 additions and 0 deletions
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10
devicemodel/hw/pci/ivshmem.c
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@ -46,6 +46,7 @@
#include "log.h" #include "log.h"
#define IVSHMEM_MMIO_BAR 0 #define IVSHMEM_MMIO_BAR 0
#define IVSHMEM_MSIX_BAR 1
#define IVSHMEM_MEM_BAR 2 #define IVSHMEM_MEM_BAR 2
#define IVSHMEM_VENDOR_ID 0x1af4 #define IVSHMEM_VENDOR_ID 0x1af4
@ -62,6 +63,9 @@
#define IVSHMEM_DOORBELL_REG 0x0c #define IVSHMEM_DOORBELL_REG 0x0c
#define IVSHMEM_RESERVED_REG 0x0f #define IVSHMEM_RESERVED_REG 0x0f
/*Size of MSIX BAR of ivshmem device should be 4KB-aligned.*/
#define IVSHMEM_MSIX_PBA_SIZE 0x1000
#define hv_land_prefix "hv:/" #define hv_land_prefix "hv:/"
#define dm_land_prefix "dm:/" #define dm_land_prefix "dm:/"
@ -151,6 +155,11 @@ create_ivshmem_from_hv(struct vmctx *ctx, struct pci_vdev *vdev,
dev.slot = PCI_BDF(vdev->bus, vdev->slot, vdev->func); dev.slot = PCI_BDF(vdev->bus, vdev->slot, vdev->func);
dev.io_addr[IVSHMEM_MMIO_BAR] = pci_get_cfgdata32(vdev, dev.io_addr[IVSHMEM_MMIO_BAR] = pci_get_cfgdata32(vdev,
PCIR_BAR(IVSHMEM_MMIO_BAR)); PCIR_BAR(IVSHMEM_MMIO_BAR));
/*MSI-x entry table BAR(BAR1)*/
addr = pci_get_cfgdata32(vdev, PCIR_BAR(IVSHMEM_MSIX_BAR));
dev.io_addr[IVSHMEM_MSIX_BAR] = addr;
addr = pci_get_cfgdata32(vdev, PCIR_BAR(IVSHMEM_MEM_BAR)); addr = pci_get_cfgdata32(vdev, PCIR_BAR(IVSHMEM_MEM_BAR));
addr |= 0x0c; /* 64bit, prefetchable */ addr |= 0x0c; /* 64bit, prefetchable */
dev.io_addr[IVSHMEM_MEM_BAR] = addr; dev.io_addr[IVSHMEM_MEM_BAR] = addr;
@ -297,6 +306,7 @@ pci_ivshmem_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
pci_set_cfgdata8(dev, PCIR_CLASS, IVSHMEM_CLASS); pci_set_cfgdata8(dev, PCIR_CLASS, IVSHMEM_CLASS);
pci_emul_alloc_bar(dev, IVSHMEM_MMIO_BAR, PCIBAR_MEM32, IVSHMEM_REG_SIZE); pci_emul_alloc_bar(dev, IVSHMEM_MMIO_BAR, PCIBAR_MEM32, IVSHMEM_REG_SIZE);
pci_emul_alloc_bar(dev, IVSHMEM_MSIX_BAR, PCIBAR_MEM32, IVSHMEM_MSIX_PBA_SIZE);
pci_emul_alloc_bar(dev, IVSHMEM_MEM_BAR, PCIBAR_MEM64, size); pci_emul_alloc_bar(dev, IVSHMEM_MEM_BAR, PCIBAR_MEM64, size);
if (is_hv_land) { if (is_hv_land) {