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HV: add hybrid_rt source code for whl-ipc-i5/i7

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Add hybrid_rt source code for whl-ipc-i5/i7.

Tracked-On: #5081
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu 2020-07-25 17:20:59 +08:00 committed by wenlingz
parent 9f3251417f
commit 310d14072b
12 changed files with 426 additions and 0 deletions
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1
misc/vm_configs/boards/whl-ipc-i5/board.c
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@ -21,6 +21,7 @@
#include <vtd.h>
#include <msr.h>
#include <pci.h>
#include <misc_cfg.h>
static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
{

1
misc/vm_configs/boards/whl-ipc-i7/board.c
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@ -21,6 +21,7 @@
#include <vtd.h>
#include <msr.h>
#include <pci.h>
#include <misc_cfg.h>
static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
{

97
misc/vm_configs/scenarios/hybrid_rt/vm_configurations.c Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_PRE_RT_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT),
.memory = {
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "PREEMPT-RT",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "RT_bzImage",
.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
consoleblank=0 tsc=reliable "
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
.pci_dev_num = VM0_CONFIG_PCI_DEV_NUM,
.pci_devs = vm0_pci_devs,
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.base_gpa = 0xFED40000UL,
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
},
#endif
},
{ /* VM1 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
.guest_flags = 0UL,
.memory = {
.start_hpa = 0UL,
.size = CONFIG_SOS_RAM_SIZE,
},
.os_config = {
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
},
{ /* VM2 */
CONFIG_POST_STD_VM(1),
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
};

39
misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
#define PRE_VM_NUM 1U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 1U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x40000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM0_CONFIG_PCI_DEV_NUM 3U
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#endif /* VM_CONFIGURATIONS_H */

32
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL
#endif /* MISC_CFG_H */

32
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/pci_dev.c Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
{
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.vdev_ops = &vhostbridge_ops,
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
PTDEV(SATA_CONTROLLER_0),
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
PTDEV(ETHERNET_CONTROLLER_0),
},
};

43
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/vbar_base.h Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \
.vbar_base[2] = 0x90000000UL
#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \
.vbar_base[2] = 0xa141d000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \
.vbar_base[1] = 0xa141b000UL, \
.vbar_base[5] = 0xa141a000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \
.vbar_base[4] = 0xa1000000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \
.vbar_base[3] = 0xa1220000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \
.vbar_base[3] = 0xa1120000UL
#endif /* VBAR_BASE_H_ */

37
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/whl-ipc-i5.config Normal file
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# Board defconfig generated by acrn-config tool
CONFIG_BOARD="whl-ipc-i5"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9600000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME=""
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y
CONFIG_RDT_ENABLED=n
CONFIG_CDP_ENABLED=n
CONFIG_HYPERV_ENABLED=y
CONFIG_IOMMU_ENFORCE_SNP=n
CONFIG_ACPI_PARSE_ENABLED=y
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
CONFIG_IOMMU_BUS_NUM=0x100
CONFIG_MAX_IOAPIC_NUM=1
CONFIG_MAX_IR_ENTRIES=256
CONFIG_MAX_PCI_DEV_NUM=96
CONFIG_MAX_IOAPIC_LINES=120
CONFIG_MAX_PT_IRQ_ENTRIES=64
CONFIG_MAX_MSIX_TABLE_NUM=64
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_LOG_BUF_SIZE=0x40000
CONFIG_NPK_LOGLEVEL_DEFAULT=5
CONFIG_MEM_LOGLEVEL_DEFAULT=5
CONFIG_LOG_DESTINATION=7
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

32
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL
#endif /* MISC_CFG_H */

32
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/pci_dev.c Normal file
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/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
{
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.vdev_ops = &vhostbridge_ops,
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
PTDEV(SATA_CONTROLLER_0),
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
PTDEV(ETHERNET_CONTROLLER_0),
},
};

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misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/vbar_base.h Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \
.vbar_base[2] = 0x90000000UL
#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \
.vbar_base[2] = 0xa141d000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \
.vbar_base[1] = 0xa141b000UL, \
.vbar_base[5] = 0xa141a000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \
.vbar_base[4] = 0xa1000000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \
.vbar_base[3] = 0xa1220000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \
.vbar_base[3] = 0xa1120000UL
#endif /* VBAR_BASE_H_ */

37
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/whl-ipc-i7.config Normal file
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# Board defconfig generated by acrn-config tool
CONFIG_BOARD="whl-ipc-i7"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9600000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME=""
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y
CONFIG_RDT_ENABLED=n
CONFIG_CDP_ENABLED=n
CONFIG_HYPERV_ENABLED=y
CONFIG_IOMMU_ENFORCE_SNP=n
CONFIG_ACPI_PARSE_ENABLED=y
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
CONFIG_IOMMU_BUS_NUM=0x100
CONFIG_MAX_IOAPIC_NUM=1
CONFIG_MAX_IR_ENTRIES=256
CONFIG_MAX_PCI_DEV_NUM=96
CONFIG_MAX_IOAPIC_LINES=120
CONFIG_MAX_PT_IRQ_ENTRIES=64
CONFIG_MAX_MSIX_TABLE_NUM=64
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_LOG_BUF_SIZE=0x40000
CONFIG_NPK_LOGLEVEL_DEFAULT=5
CONFIG_MEM_LOGLEVEL_DEFAULT=5
CONFIG_LOG_DESTINATION=7
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3