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https://github.com/projectacrn/acrn-hypervisor.git
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dm: passthru: msi/msix handling revisit
Currently, the emulation of pci msi/msix can be handled by hypervisor code. The logic in dm passthru driver can be simplified. This patch remaps msix table to usersapce in DM passthru driver. 1. The access to the msix table in passthru driver will be trapped, and emulated by hv code. 2. The access to the config space in passthru driver will be trapped, and emulated by hv code. So dm passthru driver no longer needs to keep the whole logic of handling msi/msix. No need to do msix table remapping in sos kernel. After the patch, the msix table ioremap code in vhm_dev.c can be removed. Tracked-On: #1782 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
This commit is contained in:
Binbin Wu
wenlingz
parent
38c117841f
commit
3363779d8d
@ -99,7 +99,9 @@ struct passthru_dev {
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} msi;
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struct {
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int capoff;
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int table_size;
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int table_size; /* page aligned size */
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void *table_pages;
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int table_offset; /* page aligned */
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} msix;
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bool pcie_cap;
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struct pcisel sel;
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@ -188,130 +190,6 @@ write_config(struct pci_device *phys_dev, long reg, int width, uint32_t data)
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return temp;
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}
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static int
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ptdev_msi_remap(struct vmctx *ctx, struct passthru_dev *ptdev,
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uint64_t addr, uint16_t msg, int maxmsgnum)
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{
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uint16_t msgctl;
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struct acrn_vm_pci_msix_remap msi_remap;
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int msi_capoff;
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uint16_t pci_command, new_command;
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int ret = 0;
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struct pci_device *phys_dev = ptdev->phys_dev;
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uint16_t virt_bdf = PCI_BDF(ptdev->dev->bus, ptdev->dev->slot,
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ptdev->dev->func);
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(void)maxmsgnum;
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if (ptdev->msi.capoff == 0)
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return -1;
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msi_capoff = ptdev->msi.capoff;
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/* disable MSI during configuration */
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msgctl = read_config(phys_dev, msi_capoff + PCIR_MSI_CTRL, 2);
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msgctl &= ~PCIM_MSICTRL_MSI_ENABLE;
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write_config(phys_dev, msi_capoff + PCIR_MSI_CTRL, 2, msgctl);
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msi_remap.phys_bdf = ptdev->phys_bdf;
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msi_remap.virt_bdf = virt_bdf;
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msi_remap.msi_data = msg;
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msi_remap.msi_addr = addr;
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msi_remap.msix = 0;
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msi_remap.msix_entry_index = 0;
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if (vm_setup_ptdev_msi(ctx, &msi_remap))
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return -1;
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write_config(phys_dev, msi_capoff + PCIR_MSI_ADDR, 4,
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(uint32_t)msi_remap.msi_addr);
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if (msgctl & PCIM_MSICTRL_64BIT) {
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write_config(phys_dev, msi_capoff + PCIR_MSI_ADDR_HIGH, 4,
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(uint32_t)(msi_remap.msi_addr >> 32));
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write_config(phys_dev, msi_capoff + PCIR_MSI_DATA_64BIT, 2,
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msi_remap.msi_data);
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} else {
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write_config(phys_dev, msi_capoff + PCIR_MSI_DATA, 2,
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msi_remap.msi_data);
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}
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if (!msg) {
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/* disable MSI */
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msgctl &= ~PCIM_MSICTRL_MSI_ENABLE;
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write_config(phys_dev, msi_capoff + PCIR_MSI_CTRL, 2, msgctl);
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/* enable INTx */
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pci_command = read_config(phys_dev, PCIR_COMMAND, 2);
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new_command = pci_command & (~PCI_COMMAND_INTX_DISABLE);
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if (new_command != pci_command)
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write_config(phys_dev, PCIR_COMMAND, 2, new_command);
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} else {
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/* disable INTx */
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pci_command = read_config(phys_dev, PCIR_COMMAND, 2);
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new_command = pci_command | PCI_COMMAND_INTX_DISABLE;
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if (new_command != pci_command)
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write_config(phys_dev, PCIR_COMMAND, 2, new_command);
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/* enalbe MSI */
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msgctl |= PCIM_MSICTRL_MSI_ENABLE;
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write_config(phys_dev, msi_capoff + PCIR_MSI_CTRL, 2, msgctl);
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}
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return ret;
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}
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static int
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ptdev_msix_remap(struct vmctx *ctx, const struct passthru_dev *ptdev,
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int index, uint64_t addr, uint32_t msg,
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uint32_t vector_control)
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{
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struct pci_device *phys_dev = ptdev->phys_dev;
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struct pci_vdev *dev = ptdev->dev;
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uint16_t msgctl;
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struct acrn_vm_pci_msix_remap msix_remap;
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int msix_capoff;
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uint16_t pci_command, new_command;
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uint16_t virt_bdf = PCI_BDF(ptdev->dev->bus, ptdev->dev->slot,
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ptdev->dev->func);
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if (!ptdev->msix.capoff)
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return -1;
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msix_capoff = ptdev->msix.capoff;
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/* disable MSI-X during configuration */
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msgctl = read_config(phys_dev, msix_capoff + PCIR_MSIX_CTRL, 2);
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msgctl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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msgctl |= PCIM_MSIXCTRL_FUNCTION_MASK;
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write_config(phys_dev, msix_capoff + PCIR_MSIX_CTRL, 2, msgctl);
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if (!dev->msix.enabled)
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return 0;
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msix_remap.phys_bdf = ptdev->phys_bdf;
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msix_remap.virt_bdf = virt_bdf;
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msix_remap.msi_data = msg;
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msix_remap.msi_addr = addr;
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msix_remap.msix = 1;
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msix_remap.msix_entry_index = index;
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if (vm_setup_ptdev_msi(ctx, &msix_remap))
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return -1;
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/* disable INTx */
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pci_command = read_config(phys_dev, PCIR_COMMAND, 2);
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new_command = pci_command | PCI_COMMAND_INTX_DISABLE;
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if (new_command != pci_command)
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write_config(phys_dev, PCIR_COMMAND, 2, new_command);
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/* Enable MSI-X & unmask function */
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msgctl &= ~PCIM_MSIXCTRL_FUNCTION_MASK;
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msgctl |= PCIM_MSIXCTRL_MSIX_ENABLE;
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write_config(phys_dev, msix_capoff + PCIR_MSIX_CTRL, 2, msgctl);
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return 0;
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}
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#ifdef FORCE_MSI_SINGLE_VECTOR
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/* Temporarily set mmc & mme to 0.
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@ -328,7 +206,7 @@ clear_mmc_mme(uint32_t *val)
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static int
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cfginit_cap(struct vmctx *ctx, struct passthru_dev *ptdev)
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{
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int i, ptr, capptr, cap, sts, caplen, table_size;
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int ptr, capptr, cap, sts, caplen;
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uint32_t u32;
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struct pci_vdev *dev;
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struct pci_device *phys_dev = ptdev->phys_dev;
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@ -408,6 +286,8 @@ cfginit_cap(struct vmctx *ctx, struct passthru_dev *ptdev)
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}
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}
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dev->msix.table_bar = -1;
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dev->msix.pba_bar = -1;
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if (ptdev->msix.capoff != 0) {
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capptr = ptdev->msix.capoff;
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@ -422,20 +302,6 @@ cfginit_cap(struct vmctx *ctx, struct passthru_dev *ptdev)
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msgctrl = pci_get_cfgdata16(dev, capptr + 2);
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dev->msix.table_count = MSIX_TABLE_COUNT(msgctrl);
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dev->msix.pba_size = PBA_SIZE(dev->msix.table_count);
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/* Allocate the emulated MSI-X table array */
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table_size = dev->msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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dev->msix.table = calloc(1, table_size);
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if (dev->msix.table == NULL) {
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warnx("%s: calloc FAIL!", __func__);
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return -1;
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}
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/* Mask all table entries */
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for (i = 0; i < dev->msix.table_count; i++) {
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dev->msix.table[i].vector_control |=
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PCIM_MSIX_VCTRL_MASK;
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}
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} else if (ptdev->msi.capoff != 0) {
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struct ic_ptdev_irq ptirq;
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@ -455,155 +321,74 @@ cfginit_cap(struct vmctx *ctx, struct passthru_dev *ptdev)
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static uint64_t
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msix_table_read(struct passthru_dev *ptdev, uint64_t offset, int size)
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{
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struct pci_vdev *dev;
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struct msix_table_entry *entry;
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uint8_t *src8;
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uint16_t *src16;
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uint32_t *src32;
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uint64_t *src64;
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uint64_t data;
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size_t entry_offset;
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int index;
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dev = ptdev->dev;
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if (dev->msix.pba_bar == dev->msix.table_bar &&
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offset >= dev->msix.pba_offset &&
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offset < dev->msix.pba_offset + dev->msix.pba_size) {
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switch (size) {
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case 1:
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src8 = (uint8_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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src8 = (uint8_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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data = *src8;
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break;
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case 2:
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src16 = (uint16_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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src16 = (uint16_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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data = *src16;
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break;
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case 4:
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src32 = (uint32_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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src32 = (uint32_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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data = *src32;
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break;
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case 8:
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src64 = (uint64_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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src64 = (uint64_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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data = *src64;
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break;
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default:
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return -1;
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}
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return data;
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}
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if (offset < dev->msix.table_offset)
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return -1;
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offset -= dev->msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= dev->msix.table_count)
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return -1;
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entry = &dev->msix.table[index];
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entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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switch (size) {
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case 1:
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src8 = (uint8_t *)((void *)entry + entry_offset);
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data = *src8;
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break;
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case 2:
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src16 = (uint16_t *)((void *)entry + entry_offset);
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data = *src16;
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break;
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case 4:
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src32 = (uint32_t *)((void *)entry + entry_offset);
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data = *src32;
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break;
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case 8:
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src64 = (uint64_t *)((void *)entry + entry_offset);
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data = *src64;
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break;
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default:
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return -1;
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}
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return data;
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}
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static void
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msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev *ptdev,
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uint64_t offset, int size, uint64_t data)
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msix_table_write(struct passthru_dev *ptdev, uint64_t offset, int size, uint64_t data)
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{
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struct pci_vdev *dev;
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struct msix_table_entry *entry;
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uint8_t *dest8;
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uint16_t *dest16;
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uint32_t *dest32;
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uint64_t *dest64;
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size_t entry_offset;
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uint32_t vector_control;
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int index;
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dev = ptdev->dev;
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if (dev->msix.pba_bar == dev->msix.table_bar &&
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offset >= dev->msix.pba_offset &&
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offset < dev->msix.pba_offset + dev->msix.pba_size) {
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switch (size) {
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case 1:
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dest8 = (uint8_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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dest8 = (uint8_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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*dest8 = data;
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break;
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case 2:
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dest16 = (uint16_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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dest16 = (uint16_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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*dest16 = data;
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break;
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case 4:
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dest32 = (uint32_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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dest32 = (uint32_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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*dest32 = data;
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break;
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case 8:
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dest64 = (uint64_t *)(dev->msix.pba_page + offset -
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dev->msix.pba_page_offset);
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dest64 = (uint64_t *)(ptdev->msix.table_pages + offset - ptdev->msix.table_offset);
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*dest64 = data;
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break;
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default:
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break;
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}
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return;
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}
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}
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if (offset < dev->msix.table_offset)
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return;
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static inline int ptdev_msix_table_bar(struct passthru_dev *ptdev)
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{
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return ptdev->dev->msix.table_bar;
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}
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offset -= dev->msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= dev->msix.table_count)
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return;
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entry = &dev->msix.table[index];
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entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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/* Only 4 byte naturally-aligned writes are supported */
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assert(size == 4);
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assert(entry_offset % 4 == 0);
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vector_control = entry->vector_control;
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dest32 = (uint32_t *)((void *)entry + entry_offset);
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*dest32 = data;
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/* If MSI-X hasn't been enabled, do nothing */
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if (dev->msix.enabled) {
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/* If the entry is masked, don't set it up */
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if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
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(vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
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(void)ptdev_msix_remap(ctx, ptdev, index,
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entry->addr, entry->msg_data,
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entry->vector_control);
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}
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}
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static inline int ptdev_msix_pba_bar(struct passthru_dev *ptdev)
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{
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return ptdev->dev->msix.pba_bar;
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}
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static int
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@ -613,13 +398,12 @@ init_msix_table(struct vmctx *ctx, struct passthru_dev *ptdev, uint64_t base)
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int error, idx;
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size_t len, remaining;
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uint32_t table_size, table_offset;
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uint32_t pba_size, pba_offset;
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vm_paddr_t start;
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struct pci_vdev *dev = ptdev->dev;
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uint16_t virt_bdf = PCI_BDF(dev->bus, dev->slot, dev->func);
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struct ic_ptdev_irq ptirq;
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assert(pci_msix_table_bar(dev) >= 0 && pci_msix_pba_bar(dev) >= 0);
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assert(ptdev_msix_table_bar(ptdev) >= 0 && ptdev_msix_pba_bar(ptdev) >= 0);
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b = ptdev->sel.bus;
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s = ptdev->sel.dev;
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@ -641,40 +425,6 @@ init_msix_table(struct vmctx *ctx, struct passthru_dev *ptdev, uint64_t base)
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start = dev->bar[idx].addr;
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remaining = dev->bar[idx].size;
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if (dev->msix.pba_bar == dev->msix.table_bar) {
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pba_offset = dev->msix.pba_offset;
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pba_size = dev->msix.pba_size;
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if (pba_offset >= table_offset + table_size ||
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table_offset >= pba_offset + pba_size) {
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/*
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* If the PBA does not share a page with the MSI-x
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* tables, no PBA emulation is required.
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*/
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dev->msix.pba_page = NULL;
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dev->msix.pba_page_offset = 0;
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} else {
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/*
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* The PBA overlaps with either the first or last
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* page of the MSI-X table region. Map the
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* appropriate page.
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*/
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if (pba_offset <= table_offset)
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dev->msix.pba_page_offset = table_offset;
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else
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dev->msix.pba_page_offset = table_offset +
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table_size - 4096;
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error = pci_device_map_range(ptdev->phys_dev,
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base + dev->msix.pba_page_offset, 4096,
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PCI_DEV_MAP_FLAG_WRITABLE, &dev->msix.pba_page);
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if (error) {
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warnx(
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"Failed to map PBA page for MSI-X on %x/%x/%x.",
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b, s, f);
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return error;
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}
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}
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}
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/* Map everything before the MSI-X table */
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if (table_offset > 0) {
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len = table_offset;
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@ -695,19 +445,27 @@ init_msix_table(struct vmctx *ctx, struct passthru_dev *ptdev, uint64_t base)
|
||||
remaining -= len;
|
||||
}
|
||||
|
||||
/* Handle MSI-X vectors and table:
|
||||
* request to alloc vector entries of MSI-X,
|
||||
* Map the MSI-X table to memory space of SOS
|
||||
/* remap real msix table (page-aligned) to user space */
|
||||
error = pci_device_map_range(ptdev->phys_dev, base, table_size,
|
||||
PCI_DEV_MAP_FLAG_WRITABLE, &ptdev->msix.table_pages);
|
||||
if (error) {
|
||||
warnx("Failed to map MSI-X table pages on %x/%x/%x", b,s,f);
|
||||
return error;
|
||||
}
|
||||
ptdev->msix.table_offset = table_offset;
|
||||
ptdev->msix.table_size = table_size;
|
||||
|
||||
/* Handle MSI-X vectors:
|
||||
* request to alloc vector entries of MSI-X.
|
||||
* Set table_paddr/table_size to 0 to skip ioremap in sos kernel.
|
||||
*/
|
||||
ptirq.type = IRQ_MSIX;
|
||||
ptirq.virt_bdf = virt_bdf;
|
||||
ptirq.phys_bdf = ptdev->phys_bdf;
|
||||
ptirq.msix.vector_cnt = dev->msix.table_count;
|
||||
ptirq.msix.table_paddr = ptdev->bar[idx].addr +
|
||||
dev->msix.table_offset;
|
||||
ptirq.msix.table_size = table_size;
|
||||
ptirq.msix.table_paddr = 0;
|
||||
ptirq.msix.table_size = 0;
|
||||
vm_set_ptdev_msix_info(ctx, &ptirq);
|
||||
ptdev->msix.table_size = table_size;
|
||||
|
||||
/* Skip the MSI-X table */
|
||||
base += table_size;
|
||||
@ -743,13 +501,10 @@ deinit_msix_table(struct vmctx *ctx, struct pci_vdev *dev)
|
||||
printf("ptdev reset msix: 0x%x-%x, vector_cnt=%d.\n",
|
||||
virt_bdf, ptdev->phys_bdf, vector_cnt);
|
||||
vm_reset_ptdev_msix_info(ctx, virt_bdf, vector_cnt);
|
||||
free(dev->msix.table);
|
||||
|
||||
if (dev->msix.pba_page != NULL) {
|
||||
if (pci_device_unmap_range(ptdev->phys_dev,
|
||||
dev->msix.pba_page, 4096))
|
||||
warnx("Failed to unmap pba page.");
|
||||
dev->msix.pba_page = NULL;
|
||||
if (ptdev->msix.table_pages) {
|
||||
pci_device_unmap_range(ptdev->phys_dev, ptdev->msix.table_pages, ptdev->msix.table_size);
|
||||
ptdev->msix.table_pages = NULL;
|
||||
}
|
||||
|
||||
/* We passthrough the pages not overlap with MSI-X table to guest,
|
||||
@ -832,7 +587,7 @@ cfginitbar(struct vmctx *ctx, struct passthru_dev *ptdev)
|
||||
return -1;
|
||||
|
||||
/* The MSI-X table needs special handling */
|
||||
if (i == pci_msix_table_bar(dev)) {
|
||||
if (i == ptdev_msix_table_bar(ptdev)) {
|
||||
error = init_msix_table(ctx, ptdev, base);
|
||||
if (error)
|
||||
return -1;
|
||||
@ -1150,7 +905,7 @@ passthru_deinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
|
||||
for (i = 0; i <= PCI_BARMAX; i++) {
|
||||
|
||||
if (ptdev->bar[i].size == 0 ||
|
||||
i == pci_msix_table_bar(dev) ||
|
||||
i == ptdev_msix_table_bar(ptdev) ||
|
||||
ptdev->bar[i].type == PCIBAR_IO)
|
||||
continue;
|
||||
|
||||
@ -1197,32 +952,6 @@ bar_access(int coff)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
msicap_access(struct passthru_dev *ptdev, int coff)
|
||||
{
|
||||
int caplen;
|
||||
|
||||
if (ptdev->msi.capoff == 0)
|
||||
return 0;
|
||||
|
||||
caplen = msi_caplen(ptdev->msi.msgctrl);
|
||||
|
||||
if (coff >= ptdev->msi.capoff && coff < ptdev->msi.capoff + caplen)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
msixcap_access(struct passthru_dev *ptdev, int coff)
|
||||
{
|
||||
if (ptdev->msix.capoff == 0)
|
||||
return 0;
|
||||
|
||||
return (coff >= ptdev->msix.capoff &&
|
||||
coff < ptdev->msix.capoff + MSIX_CAPLEN);
|
||||
}
|
||||
|
||||
static int
|
||||
passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
|
||||
int coff, int bytes, uint32_t *rv)
|
||||
@ -1234,7 +963,7 @@ passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
|
||||
/*
|
||||
* PCI BARs and MSI capability is emulated.
|
||||
*/
|
||||
if (bar_access(coff) || msicap_access(ptdev, coff))
|
||||
if (bar_access(coff))
|
||||
return -1;
|
||||
|
||||
/* INTLINE/INTPIN/MINGNT/MAXLAT need to be hacked */
|
||||
@ -1260,11 +989,9 @@ static int
|
||||
passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
|
||||
int coff, int bytes, uint32_t val)
|
||||
{
|
||||
int error, msix_table_entries, i;
|
||||
struct passthru_dev *ptdev;
|
||||
|
||||
ptdev = dev->arg;
|
||||
error = 1;
|
||||
|
||||
/*
|
||||
* PCI BARs are emulated
|
||||
@ -1276,51 +1003,6 @@ passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
|
||||
if (coff >= PCIR_INTLINE && coff <= PCIR_MAXLAT)
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* MSI capability is emulated
|
||||
*/
|
||||
if (msicap_access(ptdev, coff)) {
|
||||
msicap_cfgwrite(dev, ptdev->msi.capoff, coff, bytes, val);
|
||||
|
||||
if ((coff - ptdev->msi.capoff) == 2) {
|
||||
|
||||
/* currently not support multiple vectors for MSI */
|
||||
if (dev->msi.maxmsgnum > 1)
|
||||
warnx("only one vector supported for MSI");
|
||||
|
||||
if (val & PCIM_MSICTRL_MSI_ENABLE) {
|
||||
error = ptdev_msi_remap(ctx, ptdev,
|
||||
dev->msi.addr, dev->msi.msg_data,
|
||||
dev->msi.maxmsgnum);
|
||||
} else {
|
||||
error = ptdev_msi_remap(ctx, ptdev,
|
||||
dev->msi.addr, 0,
|
||||
dev->msi.maxmsgnum);
|
||||
}
|
||||
|
||||
if (error != 0)
|
||||
err(1, "ptdev_msi_remap");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (msixcap_access(ptdev, coff)) {
|
||||
msixcap_cfgwrite(dev, ptdev->msix.capoff, coff, bytes, val);
|
||||
if (dev->msix.enabled) {
|
||||
msix_table_entries = dev->msix.table_count;
|
||||
for (i = 0; i < msix_table_entries; i++) {
|
||||
error = ptdev_msix_remap(ctx, ptdev, i,
|
||||
dev->msix.table[i].addr,
|
||||
dev->msix.table[i].msg_data,
|
||||
dev->msix.table[i].vector_control);
|
||||
|
||||
if (error)
|
||||
err(1, "ptdev_msix_remap");
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
write_config(ptdev->phys_dev, coff, bytes, val);
|
||||
|
||||
return 0;
|
||||
@ -1335,8 +1017,8 @@ passthru_write(struct vmctx *ctx, int vcpu, struct pci_vdev *dev, int baridx,
|
||||
|
||||
ptdev = dev->arg;
|
||||
|
||||
if (baridx == pci_msix_table_bar(dev)) {
|
||||
msix_table_write(ctx, vcpu, ptdev, offset, size, value);
|
||||
if (baridx == ptdev_msix_table_bar(ptdev)) {
|
||||
msix_table_write(ptdev, offset, size, value);
|
||||
} else {
|
||||
assert(dev->bar[baridx].type == PCIBAR_IO);
|
||||
bzero(&pio, sizeof(struct iodev_pio_req));
|
||||
@ -1359,7 +1041,7 @@ passthru_read(struct vmctx *ctx, int vcpu, struct pci_vdev *dev, int baridx,
|
||||
|
||||
ptdev = dev->arg;
|
||||
|
||||
if (baridx == pci_msix_table_bar(dev)) {
|
||||
if (baridx == ptdev_msix_table_bar(ptdev)) {
|
||||
val = msix_table_read(ptdev, offset, size);
|
||||
} else {
|
||||
assert(dev->bar[baridx].type == PCIBAR_IO);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user