HV: enable L1 cache flush when VM entry

- flush L1 cache before VM entry only on platform
   affected by L1TF
 - flush operation is configurable by below MACRO:
    --CONFIG_L1D_FLUSH_VMENTRY_ENABLED

Tracked-On: #1672
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>

hypervisor/include/arch/x86/cpu.h

@@ -324,6 +324,7 @@ void cpu_secondary_init(void);
 void start_cpus(void);
 void stop_cpus(void);
 void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
+void cpu_l1d_flush(void);
 
 /* Read control register */
 #define CPU_CR_READ(cr, result_ptr)				\