From 34c75a0b60dcb59969490cf9010ce39cd5516a4e Mon Sep 17 00:00:00 2001
From: Sainath Grandhi <sainath.grandhi@intel.com>
Date: Mon, 18 Nov 2019 16:46:27 -0800
Subject: [PATCH] doc: Add multiple PCI segments as known limitation for
 hypervisor

ACRN does not support multiple PCI segments in its current form.
This patch adds support for mutliple PCI segments as a limitation
for ACRN in reference docs.

Tracked-On: #4134
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
---
 doc/reference/hardware.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/doc/reference/hardware.rst b/doc/reference/hardware.rst
index 3183c915b..8d826ea6d 100644
--- a/doc/reference/hardware.rst
+++ b/doc/reference/hardware.rst
@@ -23,6 +23,10 @@ Minimum Requirements for Processor
 **********************************
 1 GB Large pages
 
+Known Limitations
+*****************
+Platforms with multiple PCI segments
+
 Verified Platforms According to ACRN Usage
 ******************************************