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hv/mod_timer: make timer into an arch-independent module

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x86/timer.[ch] was moved to the common directory largely unchanged.

x86 specific code now resides in x86/tsc_deadline_timer.c and its
interface was defined in hw/hw_timer.h. The interface defines two
functions: init_hw_timer() and set_hw_timeout() that provides HW
specific initialization and timer interrupt source.

Other than these two functions, the timer module is largely arch
agnostic.

Tracked-On: #5920
Signed-off-by: Rong Liu <rong2.liu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Liang Yi 2021-04-12 13:40:00 +08:00 committed by wenlingz
parent 51204a8d11
commit 3547c9cd23
13 changed files with 83 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/acrn.doxyfile
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@ -809,7 +809,6 @@ INPUT = custom-doxygen/mainpage.md \
../hypervisor/include/arch/x86/asm/guest/vcpu.h \
../hypervisor/include/arch/x86/asm/guest/virtual_cr.h \
../hypervisor/include/arch/x86/asm/tsc.h \
../hypervisor/include/arch/x86/asm/timer.h \
../hypervisor/include/arch/x86/asm/ioapic.h \
../hypervisor/include/arch/x86/asm/lapic.h \
../hypervisor/include/lib/crypto/crypto_api.h \
@ -820,6 +819,7 @@ INPUT = custom-doxygen/mainpage.md \
../hypervisor/include/common/irq.h \
../hypervisor/include/common/ticks.h \
../hypervisor/include/common/delay.h \
../hypervisor/include/common/timer.h \
../hypervisor/include/common/ptdev.h \
../hypervisor/include/public/acrn_common.h \
../hypervisor/include/public/acrn_hv_defs.h \

3
hypervisor/Makefile
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@ -220,7 +220,7 @@ HW_C_SRCS += arch/x86/nmi.c
HW_C_SRCS += arch/x86/exception.c
HW_C_SRCS += arch/x86/irq.c
HW_C_SRCS += arch/x86/tsc.c
HW_C_SRCS += arch/x86/timer.c
HW_C_SRCS += arch/x86/tsc_deadline_timer.c
HW_C_SRCS += arch/x86/vmx.c
HW_C_SRCS += arch/x86/cpu_state_tbl.c
HW_C_SRCS += arch/x86/pm.c
@ -231,6 +231,7 @@ HW_C_SRCS += arch/x86/rdt.c
HW_C_SRCS += arch/x86/sgx.c
HW_C_SRCS += common/ticks.c
HW_C_SRCS += common/delay.c
HW_C_SRCS += common/timer.c
HW_C_SRCS += common/irq.c
HW_C_SRCS += common/softirq.c
HW_C_SRCS += common/schedule.c

1
hypervisor/arch/x86/cpu.c
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@ -32,6 +32,7 @@
#include <ivshmem.h>
#include <asm/rtcm.h>
#include <reloc.h>
#include <asm/tsc.h>
#include <ticks.h>
#include <delay.h>

1
hypervisor/arch/x86/pm.c
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@ -17,6 +17,7 @@
#include <asm/ioapic.h>
#include <asm/vtd.h>
#include <asm/lapic.h>
#include <asm/tsc.h>
#include <delay.h>
struct cpu_context cpu_ctx;

50
hypervisor/arch/x86/tsc_deadline_timer.c Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <types.h>
#include <softirq.h>
#include <irq.h>
#include <logmsg.h>
#include <asm/cpu.h>
#include <asm/msr.h>
#include <asm/irq.h>
#include <asm/apicreg.h>
#include <hw/hw_timer.h>
/* run in interrupt context */
static void timer_expired_handler(__unused uint32_t irq, __unused void *data)
{
fire_softirq(SOFTIRQ_TIMER);
}
void set_hw_timeout(uint64_t timeout)
{
msr_write(MSR_IA32_TSC_DEADLINE, timeout);
}
void init_hw_timer(void)
{
int32_t retval = 0;
if (get_pcpu_id() == BSP_CPU_ID) {
retval = request_irq(TIMER_IRQ, (irq_action_t)timer_expired_handler, NULL, IRQF_NONE);
if (retval < 0) {
pr_err("Timer setup failed");
}
}
if (retval >= 0) {
uint32_t val = TIMER_VECTOR;
val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
/* SDM 10.5.4.1: In x2APIC mode, the processor ensures the
ordering of this write and any subsequent WRMSR to the
deadline; no fencing is required. */
/* disarm timer */
msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
}
}

32
hypervisor/arch/x86/timer.c → hypervisor/common/timer.c
View File

@ -15,6 +15,7 @@
#include <trace.h>
#include <asm/irq.h>
#include <ticks.h>
#include <hw/hw_timer.h>
#define MAX_TIMER_ACTIONS 32U
#define MIN_TIMER_PERIOD_US 500U
@ -29,12 +30,6 @@ static void run_timer(const struct hv_timer *timer)
TRACE_2L(TRACE_TIMER_ACTION_PCKUP, timer->fire_tsc, 0UL);
}
/* run in interrupt context */
static void tsc_deadline_handler(__unused uint32_t irq, __unused void *data)
{
fire_softirq(SOFTIRQ_TIMER);
}
static inline void update_physical_timer(struct per_cpu_timers *cpu_timer)
{
struct hv_timer *timer = NULL;
@ -127,26 +122,13 @@ static void init_percpu_timer(uint16_t pcpu_id)
INIT_LIST_HEAD(&cpu_timer->timer_list);
}
static void init_tsc_deadline_timer(void)
{
uint32_t val;
val = TIMER_VECTOR;
val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
cpu_memory_barrier();
/* disarm timer */
msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
}
static void timer_softirq(uint16_t pcpu_id)
{
struct per_cpu_timers *cpu_timer;
struct hv_timer *timer;
const struct list_head *pos, *n;
uint32_t tries = MAX_TIMER_ACTIONS;
uint64_t current_tsc = rdtsc();
uint64_t current_tsc = cpu_ticks();
/* handle passed timer */
cpu_timer = &per_cpu(cpu_timers, pcpu_id);
@ -183,20 +165,12 @@ static void timer_softirq(uint16_t pcpu_id)
void timer_init(void)
{
uint16_t pcpu_id = get_pcpu_id();
int32_t retval = 0;
init_percpu_timer(pcpu_id);
if (pcpu_id == BSP_CPU_ID) {
register_softirq(SOFTIRQ_TIMER, timer_softirq);
retval = request_irq(TIMER_IRQ, (irq_action_t)tsc_deadline_handler, NULL, IRQF_NONE);
if (retval < 0) {
pr_err("Timer setup failed");
}
}
if (retval >= 0) {
init_tsc_deadline_timer();
}
init_hw_timer();
}

2
hypervisor/debug/console.c
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@ -8,7 +8,7 @@
#include <pci.h>
#include <uart16550.h>
#include <shell.h>
#include <asm/timer.h>
#include <timer.h>
#include <ticks.h>
#include <vuart.h>
#include <logmsg.h>

2
hypervisor/include/arch/x86/asm/guest/vlapic.h
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@ -31,7 +31,7 @@
#define VLAPIC_H
#include <asm/page.h>
#include <asm/timer.h>
#include <timer.h>
#include <asm/apicreg.h>
/**

2
hypervisor/include/arch/x86/asm/per_cpu.h
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@ -10,12 +10,12 @@
#include <types.h>
#include <sbuf.h>
#include <irq.h>
#include <timer.h>
#include <profiling.h>
#include <logmsg.h>
#include <schedule.h>
#include <asm/notify.h>
#include <asm/page.h>
#include <asm/timer.h>
#include <asm/gdt.h>
#include <asm/security.h>
#include <asm/vm_config.h>

2
hypervisor/include/common/ptdev.h
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@ -8,7 +8,7 @@
#define PTDEV_H
#include <list.h>
#include <asm/lib/spinlock.h>
#include <asm/timer.h>
#include <timer.h>
enum intx_ctlr {

2
hypervisor/include/common/schedule.h
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@ -8,7 +8,7 @@
#define SCHEDULE_H
#include <asm/lib/spinlock.h>
#include <lib/list.h>
#include <asm/timer.h>
#include <timer.h>
#define NEED_RESCHEDULE (1U)

10
hypervisor/include/arch/x86/asm/timer.h → hypervisor/include/common/timer.h
View File

@ -4,11 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef TIMER_H
#define TIMER_H
#ifndef COMMON_TIMER_H
#define COMMON_TIMER_H
#include <list.h>
#include <asm/tsc.h>
#include <ticks.h>
/**
* @brief Timer
@ -86,7 +86,7 @@ static inline void initialize_timer(struct hv_timer *timer,
*/
static inline bool timer_expired(const struct hv_timer *timer)
{
return ((timer->fire_tsc == 0UL) || (rdtsc() >= timer->fire_tsc));
return ((timer->fire_tsc == 0UL) || (cpu_ticks() >= timer->fire_tsc));
}
/**
@ -135,4 +135,4 @@ void timer_init(void);
* @}
*/
#endif /* TIMER_H */
#endif /* COMMON_TIMER_H */

15
hypervisor/include/hw/hw_timer.h Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef HW_TIMER_H
#define HW_TIMER_H
#include <types.h>
void set_hw_timeout(uint64_t timeout);
void init_hw_timer(void);
#endif