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hv: riscv: Add initial vsbi framework

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Adds initial vsbi framework.

Tracked-On: #8841
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This commit is contained in:
Haicheng Li
2025-10-20 10:36:12 +00:00
committed by acrnsi-robot
parent bae19f5f1f
commit 35f9680d30
9 changed files with 172 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hypervisor/include/arch/riscv/asm/guest/vm.h
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@@ -11,12 +11,16 @@
#include <vuart.h>
#include <fdt_api.h>
#include <asm/guest/vsbi.h>
#define INVALID_PIO_IDX -1U
#define UART_PIO_IDX0 INVALID_PIO_IDX
/* FIXME: dummy. to be implemented later */
#define EMUL_PIO_IDX_MAX 1U
struct vm_arch {
const struct acrn_vsbi_extension *vsbi_exts[MAX_NUM_SUPPORTED_VSBI_EXT];
uint16_t n_vsbi_exts;
};
struct acrn_vcpu;

33
hypervisor/include/arch/riscv/asm/guest/vsbi.h Normal file
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@@ -0,0 +1,33 @@
/*
* Copyright (C) 2018-2025 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RISCV_VSBI_H
#define RISCV_VSBI_H
#include <types.h>
#define MAX_NUM_SUPPORTED_VSBI_EXT 8
#define MAX_VSBI_EXTENSION_NAME 16
struct vsbi_ret {
uint64_t value;
bool vcpu_retain_pc;
};
struct acrn_vsbi_extension {
const char *name;
uint64_t eid_start;
uint64_t eid_end;
int32_t (*handler)(struct acrn_vcpu *vcpu, uint64_t eid,
uint64_t fid, uint64_t *args, struct vsbi_ret *out);
int32_t (*probe)(struct acrn_vm *vm);
};
int32_t vsbi_exit_handler(struct acrn_vcpu *vcpu);
void init_vsbi(struct acrn_vm *vm);
#endif /* RISCV_VSBI_H */

23
hypervisor/include/arch/riscv/asm/sbi.h
View File

@@ -60,6 +60,14 @@ enum sbi_eid {
#define SBI_HSM_FID_HART_GET_STATUS 0x2
#define SBI_HSM_FID_HART_SUSPEND 0x3
#define SBI_HSM_STATE_STARTED 0x0
#define SBI_HSM_STATE_STOPPED 0x1
#define SBI_HSM_STATE_START_PENDING 0x2
#define SBI_HSM_STATE_STOP_PENDING 0x3
#define SBI_HSM_STATE_SUSPENDED 0x4
#define SBI_HSM_STATE_SUSPEND_PENDING 0x5
#define SBI_HSM_STATE_RESUME_PENDING 0x6
/* SBI function IDs for MPXY extension*/
#define SBI_MPXY_FID_GET_SHM_SIZE 0x0
#define SBI_MPXY_FID_SET_SHM 0x1
@@ -70,6 +78,17 @@ enum sbi_eid {
#define SBI_MPXY_FID_SEND_MSG_WITHOUT_RESP 0x6
#define SBI_MPXY_FID_GET_NOTFICATION_EVENTS 0x7
/* SBI function IDs for SRST extension */
#define SBI_EXT_SRST_RESET 0x0
#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
#define SBI_SRST_RESET_REASON_NONE 0x0
#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
/* SBI return error codes */
#define SBI_SUCCESS 0
#define SBI_ERR_FAILED -1
@@ -103,4 +122,8 @@ void send_dest_ipi_mask(uint64_t dest_mask, __unused uint32_t msg_type);
int sbi_set_timer(uint64_t stime_value);
sbiret sbi_ecall(uint64_t arg0, uint64_t arg1, uint64_t arg2,
uint64_t arg3, uint64_t arg4, uint64_t arg5,
uint64_t func, uint64_t ext);
#endif /* RISCV_SBI_H */