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acrn-config: modify epc_section to configurable="0"

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1. modify epc_section to configurable="0".
2. add 'idle=halt' for sos bootargs to impove performance.

Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu
2020-04-20 09:51:16 +08:00
committed by wenlingz
parent d4236bc02d
commit 369547aa63
35 changed files with 87 additions and 87 deletions
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6
misc/acrn-config/xmls/config-xmls/apl-up2/sdc.xml
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@@ -87,7 +87,7 @@
<board_private>
<rootfs desc="rootfs for Linux kernel">/dev/mmcblk0p3</rootfs>
<bootargs desc="Specify kernel boot arguments">
rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 idle=halt
i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01010F i915.domain_plane_owners=0x011111110000 i915.enable_gvt=1
hvlog=2M@0x5de00000 memmap=0x600000$0x5da00000 ramoops.mem_address=0x5da00000 ramoops.mem_size=0x400000 ramoops.console_size=0x200000
reboot_panic=p,w module_blacklist=dwc3_pci i915.enable_guc=0x02 cma=64M@0-
@@ -106,7 +106,7 @@
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section desc="epc section">
<epc_section configurable="0" desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
</epc_section>
@@ -131,7 +131,7 @@
<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
<pcpu_id>3</pcpu_id>
</vcpu_affinity>
<epc_section desc="epc section">
<epc_section configurable="0" desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
</epc_section>