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acrn-config: update tpm config source code for hybrid_rt on ehl

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enable tpm2 config source code for hybrid_rt scenario on ehl board.

Tracked-On: #5506

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
This commit is contained in:
Shuang Zheng 2020-12-02 14:00:34 +00:00 committed by wenlingz
parent 5ea9c55145
commit 376b90d40a
8 changed files with 53 additions and 95 deletions
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68
misc/vm_configs/boards/ehl-crb-b/board.c
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@ -100,73 +100,7 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES] = {
{
.value.clos_mask = CLOS_MASK_0,
.msr_index = MSR_IA32_L2_MASK_BASE + 0,
},
{
.value.clos_mask = CLOS_MASK_1,
.msr_index = MSR_IA32_L2_MASK_BASE + 1,
},
{
.value.clos_mask = CLOS_MASK_2,
.msr_index = MSR_IA32_L2_MASK_BASE + 2,
},
{
.value.clos_mask = CLOS_MASK_3,
.msr_index = MSR_IA32_L2_MASK_BASE + 3,
},
{
.value.clos_mask = CLOS_MASK_4,
.msr_index = MSR_IA32_L2_MASK_BASE + 4,
},
{
.value.clos_mask = CLOS_MASK_5,
.msr_index = MSR_IA32_L2_MASK_BASE + 5,
},
{
.value.clos_mask = CLOS_MASK_6,
.msr_index = MSR_IA32_L2_MASK_BASE + 6,
},
{
.value.clos_mask = CLOS_MASK_7,
.msr_index = MSR_IA32_L2_MASK_BASE + 7,
},
{
.value.clos_mask = CLOS_MASK_8,
.msr_index = MSR_IA32_L2_MASK_BASE + 8,
},
{
.value.clos_mask = CLOS_MASK_9,
.msr_index = MSR_IA32_L2_MASK_BASE + 9,
},
{
.value.clos_mask = CLOS_MASK_10,
.msr_index = MSR_IA32_L2_MASK_BASE + 10,
},
{
.value.clos_mask = CLOS_MASK_11,
.msr_index = MSR_IA32_L2_MASK_BASE + 11,
},
{
.value.clos_mask = CLOS_MASK_12,
.msr_index = MSR_IA32_L2_MASK_BASE + 12,
},
{
.value.clos_mask = CLOS_MASK_13,
.msr_index = MSR_IA32_L2_MASK_BASE + 13,
},
{
.value.clos_mask = CLOS_MASK_14,
.msr_index = MSR_IA32_L2_MASK_BASE + 14,
},
{
.value.clos_mask = CLOS_MASK_15,
.msr_index = MSR_IA32_L2_MASK_BASE + 15,
},
};
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif

6
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/VM0/dsdt.asl
View File

@ -72,6 +72,10 @@ DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
)
})
}
Name (_S5, Package ()
{
0x05,
Zero,
})
}

47
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/VM0/facp.asl
View File

@ -9,9 +9,9 @@
*/
[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[0004] Table Length : 000000F4
[0001] Revision : 03
[0001] Checksum : 28
[0004] Table Length : 0000010C
[0001] Revision : 05
[0001] Checksum : 00
[0006] Oem ID : "ACRN "
[0008] Oem Table ID : "ACRNFADT"
[0004] Oem Revision : 00000001
@ -19,7 +19,7 @@
[0004] Asl Compiler Revision : 20190703
[0004] FACS Address : 00000000
[0004] DSDT Address : 7FF00200
[0004] DSDT Address : 7FF00240
[0001] Model : 00
[0001] PM Profile : 00 [Unspecified]
[0002] SCI Interrupt : 0000
@ -28,16 +28,16 @@
[0001] ACPI Disable Value : 00
[0001] S4BIOS Command : 00
[0001] P-State Control : 00
[0004] PM1A Event Block Address : 00001800
[0004] PM1A Event Block Address : 00000000
[0004] PM1B Event Block Address : 00000000
[0004] PM1A Control Block Address : 00001804
[0004] PM1A Control Block Address : 00000000
[0004] PM1B Control Block Address : 00000000
[0004] PM2 Control Block Address : 00000000
[0004] PM Timer Block Address : 00000000
[0004] GPE0 Block Address : 00000000
[0004] GPE1 Block Address : 00000000
[0001] PM1 Event Block Length : 04
[0001] PM1 Control Block Length : 02
[0001] PM1 Event Block Length : 00
[0001] PM1 Control Block Length : 00
[0001] PM2 Control Block Length : 00
[0001] PM Timer Block Length : 00
[0001] GPE0 Block Length : 00
@ -61,18 +61,18 @@
PCIe ASPM Not Supported (V4) : 0
CMOS RTC Not Present (V5) : 0
[0001] Reserved : 00
[0004] Flags (decoded below) : 00001125
[0004] Flags (decoded below) : 00000000
WBINVD instruction is operational (V1) : 1
WBINVD flushes all caches (V1) : 0
All CPUs support C1 (V1) : 1
C2 works on MP system (V1) : 0
Control Method Power Button (V1) : 0
Control Method Sleep Button (V1) : 1
Control Method Sleep Button (V1) : 0
RTC wake not in fixed reg space (V1) : 0
RTC can wake system from S4 (V1) : 0
32-bit PM Timer (V1) : 1
Docking Supported (V1) : 0
Reset Register Supported (V2) : 0
Reset Register Supported (V2) : 1
Sealed Case (V3) : 0
Headless - No Video (V3) : 1
Use native instr after SLP_TYPx (V3) : 0
@ -82,17 +82,17 @@
Remote Power-on capable (V4) : 0
Use APIC Cluster Model (V4) : 0
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[0012] Reset Register : [Generic Address Structure]
[0001] Space ID : 00 [SystemMemory]
[0001] Bit Width : 00
[0001] Space ID : 01 [SystemIO]
[0001] Bit Width : 08
[0001] Bit Offset : 00
[0001] Encoded Access Width : 00 [Undefined/Legacy]
[0008] Address : 0000000000000000
[0001] Encoded Access Width : 01 [Byte Access:8]
[0008] Address : 0000000000000CF9
[0001] Value to cause reset : 00
[0001] Value to cause reset : 0E
[0002] ARM Flags (decoded below) : 0000
PSCI Compliant : 0
Must use HVC for PSCI : 0
@ -155,3 +155,16 @@ Use APIC Physical Destination Mode (V4) : 0
[0001] Bit Offset : 00
[0001] Encoded Access Width : 00 [Undefined/Legacy]
[0008] Address : 0000000000000000
[0012] Sleep Control Register : [Generic Address Structure]
[0001] Space ID : 01 [SystemIO]
[0001] Bit Width : 08
[0001] Bit Offset : 00
[0001] Encoded Access Width : 01 [Byte Access:8]
[0008] Address : 0000000000000400
[0012] Sleep Status Register : [Generic Address Structure]
[0001] Space ID : 01 [SystemIO]
[0001] Bit Width : 08
[0001] Bit Offset : 00
[0001] Encoded Access Width : 01 [Byte Access:8]
[0008] Address : 0000000000000401

4
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/VM0/xsdt.asl
View File

@ -19,6 +19,6 @@
[0004] Asl Compiler Revision : 20190703
[0008] ACPI Table Address 0 : 000000007FF00100
[0008] ACPI Table Address 1 : 000000007FF00400
[0008] ACPI Table Address 2 : 000000007FF00440
[0008] ACPI Table Address 1 : 000000007FF00440
[0008] ACPI Table Address 2 : 000000007FF00480
[0008] ACPI Table Address 3 : 000000007FF01100

1
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/ehl-crb-b.config
View File

@ -10,7 +10,6 @@ CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_IVSHMEM_ENABLED=y
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME=""
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y

11
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h
View File

@ -7,7 +7,7 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/mmcblk0p2 "
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
@ -76,12 +76,17 @@
#define VM3_VCPU_CLOS {0U}
#endif
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_BASE_ADDR_GPA 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL
#define VM0_CONFIG_PCI_DEV_NUM 4U
#define VM2_CONFIG_PCI_DEV_NUM 1U
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda2 console=ttyS0 \
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
consoleblank=0 tsc=reliable"
consoleblank=0 tsc=reliable reboot=acpi"
#define VM0_PT_INTX_NUM 0U

1
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/pci_dev.c
View File

@ -22,6 +22,7 @@
* TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
* to simplify the code.
*/
struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
{
.emu_type = PCI_DEV_TYPE_HVEMUL,

10
misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/vbar_base.h
View File

@ -7,6 +7,10 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \
.vbar_base[1] = 0x80001000UL, \
.vbar_base[2] = 0x8020000cUL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
.vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL
@ -66,7 +70,8 @@
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL, \
.vbar_base[2] = 0x80002000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
.vbar_base[2] = 0x834f2000UL
@ -78,7 +83,4 @@
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x100000000UL, \
.vbar_base[2] = 0x10020000cUL
#endif /* VBAR_BASE_H_ */