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hv: riscv: implement arch-specific IRQ functions

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Implement the following functions required by the common IRQ framework:

 - void arch_init_irq_descs(struct irq_desc *descs);
 - void arch_setup_irqs(void);
 - void arch_init_interrupt(uint16_t pcpu_id);
 - void arch_free_irq(uint32_t irq);
 - bool arch_request_irq(uint32_t irq);
 - void arch_pre_irq(const struct irq_desc *desc);
 - void arch_post_irq(const struct irq_desc *desc);

Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This commit is contained in:
Shiqing Gao
2025-10-15 13:08:44 +08:00
committed by acrnsi-robot
parent 672093a940
commit 386a1df60d
2 changed files with 351 additions and 3 deletions
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72
hypervisor/include/arch/riscv/asm/irq.h
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@@ -14,8 +14,41 @@
#define IPI_NOTIFY_CPU 0U
/* TODO: to be implemented in later patches when integration with the common IRQ framework is done.*/
#define NR_IRQS 0U
/* CPU-local interrupt count (room for standard causes) */
#define IRQ_NUM_CPU_DOMAIN 16U
/*
* TODO: Abstract IRQ_NUM_PLIC_DOMAIN from the device tree.
*
* Example PLIC device tree entry (as emulated by QEMU):
* plic@c000000 {
* ...
* riscv,ndev = <0x0000005f>;
* ...
* };
*
* Add 1 to 0x0000005f since interrupt ID 0 is reserved to mean "no interrupt",
* per the PLIC specification.
*/
#define IRQ_NUM_PLIC_DOMAIN 0x60U
/*
* Future: IRQ_NUM_APLIC_DOMAIN
*
* Example APLIC device tree entry:
* aplic1: interrupt-controller@d000000 {
* ...
* riscv,num-sources = <63>;
* ...
* };
*/
#define NR_IRQS (IRQ_NUM_CPU_DOMAIN + IRQ_NUM_PLIC_DOMAIN)
struct riscv_irq_data {
uint32_t acrn_irq;
/* Can be extended when PROFILING_ON is supported, similar to "struct x86_irq_data". */
};
struct intr_excp_ctx {
struct cpu_regs regs;
@@ -23,4 +56,39 @@ struct intr_excp_ctx {
void init_interrupt(uint16_t pcpu_id);
/* IRQ domain names */
#define RISCV_IRQD_CPU "cpu-intc"
/*
* For non-CPU IRQ domains, the domain name can be derived from the device tree
* during the IRQ chip probe.
*
* Example device tree:
*
* IRQ chip:
* plic0: interrupt-controller@c000000 {
* compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
* ...
* };
*
* Device:
* i2c0: i2c@10030000 {
* ...
* interrupt-parent = <&plic0>;
* ...
* };
*
* The IRQ domain name can be taken from the 'interrupt-parent' label (e.g. "plic0"),
* or derived by combining it with one of the compatible strings when only a phandle
* is provided as the 'interrupt-parent'. This helps uniquely identify each IRQ
* domain instance.
*/
/* Domain registration & flat mapping helpers */
bool riscv_register_irq_domain(const char *name, uint32_t irq_num);
uint32_t riscv_domain_get_acrn_irq(const char *name, uint32_t src_id);
/* Helper to verify that the IRQ is registered and valid during interrupt dispatch. */
bool riscv_is_valid_acrn_irq(uint32_t irq);
#endif /* RISCV_IRQ_H */