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hv: riscv: fix local_irq_save to only clear SIE bit

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local_irq_save() is intended to read and clear the SIE bit in
sstatus (disabling interrupts). The current implementation mistakenly
clears all bits in sstatus.

This patch corrects the inline assembly so that only the SIE bit is affected,
ensuring proper interrupt save/disable semantics on RISC-V.

Fixes: a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h")

Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Shiqing Gao
2025-09-22 16:39:12 +08:00
committed by acrnsi-robot
parent fc495b946a
commit 395a7c44bc
1 changed files with 1 additions and 1 deletions
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2
hypervisor/include/arch/riscv/asm/cpu.h
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@@ -133,7 +133,7 @@ static inline void arch_asm_pause(void)
#define local_irq_save(x) \
({ \
uint32_t val = 0U; \
asm volatile("csrrc %0, sstatus, 0\n" : "=r"(val) : "i"(SSTATUS_SIE) : "memory"); \
asm volatile("csrrc %0, sstatus, %1\n" : "=r"(val) : "i"(SSTATUS_SIE) : "memory"); \
*(uint32_t *)(x) = val; \
})