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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-08-02 08:19:16 +00:00
HV: make io_write_fn_t return true or false
This patch makes io_write_fn_t return true or false instead of void. Returning true means that the handler in HV process the request completely. Returning false means that we need to re-inject the request to DM after processing it in HV. Tracked-On: #2865 Signed-off-by: Kaige Fu <kaige.fu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -217,7 +217,13 @@ hv_emulate_pio(const struct acrn_vcpu *vcpu, struct io_request *io_req)
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if (pio_req->direction == REQUEST_WRITE) {
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if (handler->io_write != NULL) {
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handler->io_write(vm, port, size, pio_req->value);
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if (!(handler->io_write(vm, port, size, pio_req->value))) {
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/*
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* If io_write return false, it indicates that we need continue
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* to emulate in DM.
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*/
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status = -ENODEV;
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}
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}
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pr_dbg("IO write on port %04x, data %08x", port, pio_req->value);
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} else {
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@ -142,7 +142,7 @@ static inline void enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val, uint32_t
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resume_vm_from_s3(vm, guest_wakeup_vec32); /* jump back to vm */
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}
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static void pm1ab_io_write(struct acrn_vm *vm, uint16_t addr, size_t width, uint32_t v)
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static bool pm1ab_io_write(struct acrn_vm *vm, uint16_t addr, size_t width, uint32_t v)
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{
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static uint32_t pm1a_cnt_ready = 0U;
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bool to_write = true;
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@ -179,6 +179,8 @@ static void pm1ab_io_write(struct acrn_vm *vm, uint16_t addr, size_t width, uint
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if (to_write) {
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pio_write(v, addr, width);
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}
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return true;
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}
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static void register_gas_io_handler(struct acrn_vm *vm, uint32_t pio_idx, const struct acpi_generic_address *gas)
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@ -161,7 +161,7 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
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vioapic_set_irqline_lock(vu->vm, vuart_com_irq, operation);
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}
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static void vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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__unused size_t width, uint32_t value)
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{
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uint16_t offset = offset_arg;
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@ -244,6 +244,8 @@ static void vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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done:
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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return true;
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}
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static uint32_t vuart_read(struct acrn_vm *vm, uint16_t offset_arg,
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@ -66,7 +66,7 @@ static uint32_t pci_cfgaddr_io_read(struct acrn_vm *vm, uint16_t addr, size_t by
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/**
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* @pre vm != NULL
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*/
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static void pci_cfgaddr_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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static bool pci_cfgaddr_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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{
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struct acrn_vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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@ -76,6 +76,8 @@ static void pci_cfgaddr_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes
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pi->cached_reg = val & PCI_REGMAX;
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pi->cached_enable = ((val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE);
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}
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return true;
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}
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static inline bool vpci_is_valid_access_offset(uint32_t offset, uint32_t bytes)
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@ -135,7 +137,7 @@ static uint32_t pci_cfgdata_io_read(struct acrn_vm *vm, uint16_t addr, size_t by
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* @pre vm->vm_id < CONFIG_MAX_VM_NUM
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* @pre (get_vm_config(vm->vm_id)->type == PRE_LAUNCHED_VM) || (get_vm_config(vm->vm_id)->type == SOS_VM)
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*/
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static void pci_cfgdata_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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static bool pci_cfgdata_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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{
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struct acrn_vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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@ -163,6 +165,8 @@ static void pci_cfgdata_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes
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}
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pci_cfg_clear_cache(pi);
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}
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return true;
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}
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/**
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@ -739,7 +739,7 @@ static uint32_t vpic_master_io_read(struct acrn_vm *vm, uint16_t addr, size_t wi
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return val;
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}
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static void vpic_master_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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static bool vpic_master_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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uint32_t v)
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{
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uint32_t val = v;
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@ -748,6 +748,8 @@ static void vpic_master_io_write(struct acrn_vm *vm, uint16_t addr, size_t width
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pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
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__func__, addr, width, val);
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}
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return true;
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}
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static int32_t vpic_slave_handler(struct acrn_vm *vm, bool in, uint16_t port,
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@ -782,7 +784,7 @@ static uint32_t vpic_slave_io_read(struct acrn_vm *vm, uint16_t addr, size_t wid
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return val;
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}
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static void vpic_slave_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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static bool vpic_slave_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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uint32_t v)
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{
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uint32_t val = v;
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@ -791,6 +793,8 @@ static void vpic_slave_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
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__func__, addr, width, val);
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}
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return true;
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}
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static int32_t vpic_elc_handler(struct acrn_vm *vm, bool in, uint16_t port, size_t bytes,
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@ -849,7 +853,7 @@ static uint32_t vpic_elc_io_read(struct acrn_vm *vm, uint16_t addr, size_t width
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return val;
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}
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static void vpic_elc_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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static bool vpic_elc_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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uint32_t v)
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{
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uint32_t val = v;
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@ -858,6 +862,8 @@ static void vpic_elc_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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pr_err("%s: write port 0x%x width=%d value 0x%x failed\n",
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__func__, addr, width, val);
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}
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return true;
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}
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static void vpic_register_io_handler(struct acrn_vm *vm)
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@ -58,16 +58,14 @@ static uint32_t vrtc_read(struct acrn_vm *vm, uint16_t addr, __unused size_t wid
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return reg;
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}
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static void vrtc_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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static bool vrtc_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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uint32_t value)
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{
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if (width != 1U)
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return;
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if (addr == CMOS_ADDR_PORT) {
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if ((width == 1U) && (addr == CMOS_ADDR_PORT)) {
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vm->vrtc_offset = value & 0x7FU;
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}
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return true;
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}
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void vrtc_init(struct acrn_vm *vm)
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@ -52,7 +52,7 @@ typedef
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uint32_t (*io_read_fn_t)(struct acrn_vm *vm, uint16_t port, size_t size);
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typedef
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void (*io_write_fn_t)(struct acrn_vm *vm, uint16_t port, size_t size, uint32_t val);
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bool (*io_write_fn_t)(struct acrn_vm *vm, uint16_t port, size_t size, uint32_t val);
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/**
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* @brief Describes a single IO handler description entry.
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