diff --git a/devicemodel/hw/pci/passthrough.c b/devicemodel/hw/pci/passthrough.c
index 4c7597b53..accd72fab 100644
--- a/devicemodel/hw/pci/passthrough.c
+++ b/devicemodel/hw/pci/passthrough.c
@@ -48,6 +48,7 @@
 #include "dm.h"
 #include "passthru.h"
 #include "ptm.h"
+#include "igd_pciids.h"
 
 /* Some audio drivers get topology data from ACPI NHLT table.
  * For such drivers, we need to copy the host NHLT table to make it
@@ -555,6 +556,36 @@ get_gpu_rsvmem_size()
 	return GPU_OPREGION_SIZE + GPU_DSM_SIZE;
 }
 
+static const struct igd_device igd_device_tbl[] = {
+	IGD_RPLP_DEVICE_IDS,
+	IGD_RPLS_DEVICE_IDS,
+	IGD_ADLN_DEVICE_IDS,
+	IGD_ADLP_DEVICE_IDS,
+	IGD_ADLS_DEVICE_IDS,
+	IGD_RKL_DEVICE_IDS,
+	IGD_TGL_DEVICE_IDS,
+	IGD_JSL_DEVICE_IDS,
+	IGD_EHL_DEVICE_IDS,
+	IGD_ICL_DEVICE_IDS,
+	IGD_CFL_DEVICE_IDS,
+	IGD_KBL_DEVICE_IDS,
+	IGD_GLK_DEVICE_IDS,
+	IGD_BXT_DEVICE_IDS,
+	IGD_SKL_DEVICE_IDS,
+	{ 0 }
+};
+
+int igd_gen(uint16_t device) {
+	const struct igd_device *entry;
+
+	for (entry = igd_device_tbl; entry->device != 0; entry++) {
+		if (entry->device == device) {
+			return entry->gen;
+		}
+	}
+	return 0;
+}
+
 /*
  * passthrough GPU DSM(Data Stolen Memory) and Opregion to guest
  */
@@ -563,59 +594,20 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
 			struct acrn_pcidev *pcidev, uint16_t device)
 {
 	uint32_t opregion_phys, dsm_mask_val;
+	int gen;
 
 	/* get opregion hpa */
 	opregion_phys = read_config(ptdev->phys_dev, PCIR_ASLS_CTL, 4);
 	gpu_opregion_hpa = opregion_phys & PCIM_ASLS_OPREGION_MASK;
 
-	switch (device) {
-	/* ElkhartLake */
-	case 0x4500:
-	case 0x4541:
-	case 0x4551:
-	case 0x4571:
-	/* TigerLake */
-	case 0x9a40:
-	case 0x9a49:
-	case 0x9a59:
-	case 0x9a60:
-	case 0x9a68:
-	case 0x9a70:
-	case 0x9a78:
-	case 0x9ac0:
-	case 0x9ac9:
-	case 0x9ad9:
-	case 0x9af8:
-	/* AlderLake */
-	case 0x4680:
-	case 0x4681:
-	case 0x4682:
-	case 0x4683:
-	case 0x4690:
-	case 0x4691:
-	case 0x4692:
-	case 0x4693:
-	case 0x4698:
-	case 0x4699:
-	/* ADL-P GT graphics */
-	case 0x4626:
-	case 0x4628:
-	case 0x462a:
-	case 0x46a0:
-	case 0x46a1:
-	case 0x46a2:
-	case 0x46a3:
-	case 0x46a6:
-	case 0x46a8:
-	case 0x46aa:
-	case 0x46b0:
-	case 0x46b1:
-	case 0x46b2:
-	case 0x46b3:
-	case 0x46c0:
-	case 0x46c1:
-	case 0x46c2:
-	case 0x46c3:
+	gen = igd_gen(device);
+	if (!gen) {
+		pr_warn("Device 8086:%04x is not an igd device in allowlist, assuming it is gen 11+. " \
+			"GVT-d may not working properly\n", device);
+		gen = 11;
+	}
+
+	if (gen >= 11) {
 		/* BDSM register has 64 bits.
 		 * bits 63:20 contains the base address of stolen memory
 		 */
@@ -634,9 +626,7 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
 		pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW1, 0);
 
 		ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_ehl_gpu;
-		break;
-	/* If on default platforms, such as KBL,WHL  */
-	default:
+	} else {
 		/* bits 31:20 contains the base address of stolen memory */
 		gpu_dsm_hpa = read_config(ptdev->phys_dev, PCIR_BDSM, 4);
 		dsm_mask_val = gpu_dsm_hpa & ~PCIM_BDSM_MASK;
@@ -646,7 +636,6 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
 		pci_set_cfgdata32(ptdev->dev, PCIR_BDSM, gpu_dsm_gpa | dsm_mask_val);
 
 		ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_def_gpu;
-		break;
 	}
 
 	gpu_opregion_gpa = gpu_dsm_gpa - GPU_OPREGION_SIZE;
diff --git a/devicemodel/include/igd_pciids.h b/devicemodel/include/igd_pciids.h
new file mode 100644
index 000000000..be1f8fcda
--- /dev/null
+++ b/devicemodel/include/igd_pciids.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright (C) 2023 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Device ids are available in linux kernel source tree and Intel website.
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h
+ * https://dgpu-docs.intel.com/devices/hardware-table.html
+ */
+
+#ifndef _IGD_PCIIDS_H_
+#define _IGD_PCIIDS_H_
+
+#include <stdint.h>
+
+struct igd_device {
+	uint16_t device;
+	int gen;
+};
+
+#define IGD_DEVICE_ENTRY(id, gen)	\
+	{ id, gen }
+
+
+/* Skylake, Gen 9 */
+#define IGD_SKL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x1906, 9),	\
+	IGD_DEVICE_ENTRY(0x1913, 9),	\
+	IGD_DEVICE_ENTRY(0x190E, 9),	\
+	IGD_DEVICE_ENTRY(0x1915, 9),	\
+	IGD_DEVICE_ENTRY(0x1902, 9),	\
+	IGD_DEVICE_ENTRY(0x190A, 9),	\
+	IGD_DEVICE_ENTRY(0x190B, 9),	\
+	IGD_DEVICE_ENTRY(0x1917, 9),	\
+	IGD_DEVICE_ENTRY(0x1916, 9),	\
+	IGD_DEVICE_ENTRY(0x1921, 9),	\
+	IGD_DEVICE_ENTRY(0x191E, 9),	\
+	IGD_DEVICE_ENTRY(0x1912, 9),	\
+	IGD_DEVICE_ENTRY(0x191A, 9),	\
+	IGD_DEVICE_ENTRY(0x191B, 9),	\
+	IGD_DEVICE_ENTRY(0x191D, 9),	\
+	IGD_DEVICE_ENTRY(0x1923, 9),	\
+	IGD_DEVICE_ENTRY(0x1926, 9),	\
+	IGD_DEVICE_ENTRY(0x1927, 9),	\
+	IGD_DEVICE_ENTRY(0x192A, 9),	\
+	IGD_DEVICE_ENTRY(0x192B, 9),	\
+	IGD_DEVICE_ENTRY(0x192D, 9),	\
+	IGD_DEVICE_ENTRY(0x1932, 9),	\
+	IGD_DEVICE_ENTRY(0x193A, 9),	\
+	IGD_DEVICE_ENTRY(0x193B, 9),	\
+	IGD_DEVICE_ENTRY(0x193D, 9)
+
+/* Apollo Lake, Gen 9 */
+#define IGD_BXT_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x0A84, 9),	\
+	IGD_DEVICE_ENTRY(0x1A84, 9),	\
+	IGD_DEVICE_ENTRY(0x1A85, 9),	\
+	IGD_DEVICE_ENTRY(0x5A84, 9),	\
+	IGD_DEVICE_ENTRY(0x5A85, 9)
+
+/* Gemini Lake, Gen 9 */
+#define IGD_GLK_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x3184, 9),	\
+	IGD_DEVICE_ENTRY(0x3185, 9)
+
+/* Kaby Lake, Gen 9 */
+#define IGD_KBL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x5906, 9),	\
+	IGD_DEVICE_ENTRY(0x5913, 9),	\
+	IGD_DEVICE_ENTRY(0x590E, 9),	\
+	IGD_DEVICE_ENTRY(0x5915, 9),	\
+	IGD_DEVICE_ENTRY(0x5902, 9),	\
+	IGD_DEVICE_ENTRY(0x5908, 9),	\
+	IGD_DEVICE_ENTRY(0x590A, 9),	\
+	IGD_DEVICE_ENTRY(0x590B, 9),	\
+	IGD_DEVICE_ENTRY(0x5916, 9),	\
+	IGD_DEVICE_ENTRY(0x5921, 9),	\
+	IGD_DEVICE_ENTRY(0x591E, 9),	\
+	IGD_DEVICE_ENTRY(0x5912, 9),	\
+	IGD_DEVICE_ENTRY(0x5917, 9),	\
+	IGD_DEVICE_ENTRY(0x591A, 9),	\
+	IGD_DEVICE_ENTRY(0x591B, 9),	\
+	IGD_DEVICE_ENTRY(0x591D, 9),	\
+	IGD_DEVICE_ENTRY(0x5926, 9),	\
+	IGD_DEVICE_ENTRY(0x5923, 9),	\
+	IGD_DEVICE_ENTRY(0x5927, 9),	\
+	IGD_DEVICE_ENTRY(0x593B, 9),	\
+	IGD_DEVICE_ENTRY(0x591C, 9),	\
+	IGD_DEVICE_ENTRY(0x87C0, 9)
+
+/* Coffee Lake/Comet Lake, Gen 9 */
+#define IGD_CFL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x87CA, 9),	\
+	IGD_DEVICE_ENTRY(0x9BA2, 9),	\
+	IGD_DEVICE_ENTRY(0x9BA4, 9),	\
+	IGD_DEVICE_ENTRY(0x9BA5, 9),	\
+	IGD_DEVICE_ENTRY(0x9BA8, 9),	\
+	IGD_DEVICE_ENTRY(0x9B21, 9),	\
+	IGD_DEVICE_ENTRY(0x9BAA, 9),	\
+	IGD_DEVICE_ENTRY(0x9BAC, 9),	\
+	IGD_DEVICE_ENTRY(0x9BC2, 9),	\
+	IGD_DEVICE_ENTRY(0x9BC4, 9),	\
+	IGD_DEVICE_ENTRY(0x9BC5, 9),	\
+	IGD_DEVICE_ENTRY(0x9BC6, 9),	\
+	IGD_DEVICE_ENTRY(0x9BC8, 9),	\
+	IGD_DEVICE_ENTRY(0x9BE6, 9),	\
+	IGD_DEVICE_ENTRY(0x9BF6, 9),	\
+	IGD_DEVICE_ENTRY(0x9B41, 9),	\
+	IGD_DEVICE_ENTRY(0x9BCA, 9),	\
+	IGD_DEVICE_ENTRY(0x9BCC, 9),	\
+	IGD_DEVICE_ENTRY(0x3E90, 9),	\
+	IGD_DEVICE_ENTRY(0x3E93, 9),	\
+	IGD_DEVICE_ENTRY(0x3E99, 9),	\
+	IGD_DEVICE_ENTRY(0x3E91, 9),	\
+	IGD_DEVICE_ENTRY(0x3E92, 9),	\
+	IGD_DEVICE_ENTRY(0x3E96, 9),	\
+	IGD_DEVICE_ENTRY(0x3E98, 9),	\
+	IGD_DEVICE_ENTRY(0x3E9A, 9),	\
+	IGD_DEVICE_ENTRY(0x3E9C, 9),	\
+	IGD_DEVICE_ENTRY(0x3E94, 9),	\
+	IGD_DEVICE_ENTRY(0x3E9B, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA9, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA5, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA6, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA7, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA8, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA1, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA4, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA0, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA3, 9),	\
+	IGD_DEVICE_ENTRY(0x3EA2, 9)
+
+/* Ice Lake, Gen 11 */
+#define IGD_ICL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x8A50, 11),	\
+	IGD_DEVICE_ENTRY(0x8A52, 11),	\
+	IGD_DEVICE_ENTRY(0x8A53, 11),	\
+	IGD_DEVICE_ENTRY(0x8A54, 11),	\
+	IGD_DEVICE_ENTRY(0x8A56, 11),	\
+	IGD_DEVICE_ENTRY(0x8A57, 11),	\
+	IGD_DEVICE_ENTRY(0x8A58, 11),	\
+	IGD_DEVICE_ENTRY(0x8A59, 11),	\
+	IGD_DEVICE_ENTRY(0x8A5A, 11),	\
+	IGD_DEVICE_ENTRY(0x8A5B, 11),	\
+	IGD_DEVICE_ENTRY(0x8A5C, 11),	\
+	IGD_DEVICE_ENTRY(0x8A70, 11),	\
+	IGD_DEVICE_ENTRY(0x8A71, 11),	\
+	IGD_DEVICE_ENTRY(0x8A51, 11),	\
+	IGD_DEVICE_ENTRY(0x8A5D, 11)
+
+/* Elkhart Lake, Gen 12 */
+#define IGD_EHL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x4541, 12),	\
+	IGD_DEVICE_ENTRY(0x4551, 12),	\
+	IGD_DEVICE_ENTRY(0x4555, 12),	\
+	IGD_DEVICE_ENTRY(0x4557, 12),	\
+	IGD_DEVICE_ENTRY(0x4570, 12),	\
+	IGD_DEVICE_ENTRY(0x4571, 12)
+
+/* Jasper Lake, Gen 12 */
+#define IGD_JSL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x4E51, 12),	\
+	IGD_DEVICE_ENTRY(0x4E55, 12),	\
+	IGD_DEVICE_ENTRY(0x4E57, 12),	\
+	IGD_DEVICE_ENTRY(0x4E61, 12),	\
+	IGD_DEVICE_ENTRY(0x4E71, 12)
+
+/* Tiger Lake, Gen 12 */
+#define IGD_TGL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x9A60, 12),	\
+	IGD_DEVICE_ENTRY(0x9A68, 12),	\
+	IGD_DEVICE_ENTRY(0x9A70, 12),	\
+	IGD_DEVICE_ENTRY(0x9A40, 12),	\
+	IGD_DEVICE_ENTRY(0x9A49, 12),	\
+	IGD_DEVICE_ENTRY(0x9A59, 12),	\
+	IGD_DEVICE_ENTRY(0x9A78, 12),	\
+	IGD_DEVICE_ENTRY(0x9AC0, 12),	\
+	IGD_DEVICE_ENTRY(0x9AC9, 12),	\
+	IGD_DEVICE_ENTRY(0x9AD9, 12),	\
+	IGD_DEVICE_ENTRY(0x9AF8, 12)
+
+/* Rocket Lake, Gen 12 */
+#define IGD_RKL_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x4C80, 12),	\
+	IGD_DEVICE_ENTRY(0x4C8A, 12),	\
+	IGD_DEVICE_ENTRY(0x4C8B, 12),	\
+	IGD_DEVICE_ENTRY(0x4C8C, 12),	\
+	IGD_DEVICE_ENTRY(0x4C90, 12),	\
+	IGD_DEVICE_ENTRY(0x4C9A, 12)
+
+/* Alder Lake-S, Gen 12 */
+#define IGD_ADLS_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x4680, 12),	\
+	IGD_DEVICE_ENTRY(0x4682, 12),	\
+	IGD_DEVICE_ENTRY(0x4688, 12),	\
+	IGD_DEVICE_ENTRY(0x468A, 12),	\
+	IGD_DEVICE_ENTRY(0x468B, 12),	\
+	IGD_DEVICE_ENTRY(0x4690, 12),	\
+	IGD_DEVICE_ENTRY(0x4692, 12),	\
+	IGD_DEVICE_ENTRY(0x4693, 12)
+
+/* Alder Lake-P, Gen 12 */
+#define IGD_ADLP_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x46A0, 12),	\
+	IGD_DEVICE_ENTRY(0x46A1, 12),	\
+	IGD_DEVICE_ENTRY(0x46A2, 12),	\
+	IGD_DEVICE_ENTRY(0x46A3, 12),	\
+	IGD_DEVICE_ENTRY(0x46A6, 12),	\
+	IGD_DEVICE_ENTRY(0x46A8, 12),	\
+	IGD_DEVICE_ENTRY(0x46AA, 12),	\
+	IGD_DEVICE_ENTRY(0x462A, 12),	\
+	IGD_DEVICE_ENTRY(0x4626, 12),	\
+	IGD_DEVICE_ENTRY(0x4628, 12),	\
+	IGD_DEVICE_ENTRY(0x46B0, 12),	\
+	IGD_DEVICE_ENTRY(0x46B1, 12),	\
+	IGD_DEVICE_ENTRY(0x46B2, 12),	\
+	IGD_DEVICE_ENTRY(0x46B3, 12),	\
+	IGD_DEVICE_ENTRY(0x46C0, 12),	\
+	IGD_DEVICE_ENTRY(0x46C1, 12),	\
+	IGD_DEVICE_ENTRY(0x46C2, 12),	\
+	IGD_DEVICE_ENTRY(0x46C3, 12)
+
+/* Alder Lake-N, Gen 12 */
+#define IGD_ADLN_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0x46D0, 12),	\
+	IGD_DEVICE_ENTRY(0x46D1, 12),	\
+	IGD_DEVICE_ENTRY(0x46D2, 12)
+
+/* Raptor Lake-S, Gen 12 */
+#define IGD_RPLS_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0xA780, 12),	\
+	IGD_DEVICE_ENTRY(0xA781, 12),	\
+	IGD_DEVICE_ENTRY(0xA782, 12),	\
+	IGD_DEVICE_ENTRY(0xA783, 12),	\
+	IGD_DEVICE_ENTRY(0xA788, 12),	\
+	IGD_DEVICE_ENTRY(0xA789, 12),	\
+	IGD_DEVICE_ENTRY(0xA78A, 12),	\
+	IGD_DEVICE_ENTRY(0xA78B, 12)
+
+/* Raptor Lake-P, Gen 12 */
+#define IGD_RPLP_DEVICE_IDS	\
+	IGD_DEVICE_ENTRY(0xA721, 12),	\
+	IGD_DEVICE_ENTRY(0xA7A1, 12),	\
+	IGD_DEVICE_ENTRY(0xA7A9, 12),	\
+	IGD_DEVICE_ENTRY(0xA720, 12),	\
+	IGD_DEVICE_ENTRY(0xA7A0, 12),	\
+	IGD_DEVICE_ENTRY(0xA7A8, 12)
+
+#endif