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hypervisor: Fix spelling and grammar mistakes.

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Tracked-On: #8533
Signed-off-by: Muhammad Qasim Abdul Majeed <qasim.majeed20@gmail.com>
This commit is contained in:
Muhammad Qasim Abdul Majeed 2023-10-23 14:04:50 +05:00 committed by acrnsi-robot
parent ce96ef6bae
commit 3be3b394ad
3 changed files with 7 additions and 7 deletions
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2
hypervisor/arch/x86/notify.c
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@ -22,7 +22,7 @@ static uint64_t smp_call_mask = 0UL;
/* run in interrupt context */ /* run in interrupt context */
static void kick_notification(__unused uint32_t irq, __unused void *data) static void kick_notification(__unused uint32_t irq, __unused void *data)
{ {
/* Notification vector is used to kick taget cpu out of non-root mode. /* Notification vector is used to kick target cpu out of non-root mode.
* And it also serves for smp call. * And it also serves for smp call.
*/ */
uint16_t pcpu_id = get_pcpu_id(); uint16_t pcpu_id = get_pcpu_id();

6
hypervisor/arch/x86/page.c
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@ -32,10 +32,10 @@ struct page *alloc_page(struct page_pool *pool)
ASSERT(page != NULL, "no page aviable!"); ASSERT(page != NULL, "no page aviable!");
page = (page != NULL) ? page : pool->dummy_page; page = (page != NULL) ? page : pool->dummy_page;
if (page == NULL) { if (page == NULL) {
/* For HV MMU pagetable mapping, we didn't use dummy page when there's no page /* For HV MMU page-table mapping, we didn't use dummy page when there's no page
* aviable in the page pool. This because we only do MMU pagetable mapping on * available in the page pool. This because we only do MMU page-table mapping on
* the early boot time and we reserve enough pages for it. After that, we would * the early boot time and we reserve enough pages for it. After that, we would
* not do any MMU pagetable mapping. We would let the system boot fail when page * not do any MMU page-table mapping. We would let the system boot fail when page
* allocation failed. * allocation failed.
*/ */
panic("no dummy aviable!"); panic("no dummy aviable!");

6
hypervisor/arch/x86/pm.c
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@ -302,7 +302,7 @@ void init_frequency_policy(void)
* This Function is to be called by each pcpu after init_cpufreq(). * This Function is to be called by each pcpu after init_cpufreq().
* It applies the frequency policy, which can be specified from boot parameters. * It applies the frequency policy, which can be specified from boot parameters.
* - cpu_perf_policy=Performance: HWP autonomous selection, between highest HWP level and * - cpu_perf_policy=Performance: HWP autonomous selection, between highest HWP level and
* lowest HWP level. If HWP is not avaliable, the frequency is fixed to highest p-state. * lowest HWP level. If HWP is not available, the frequency is fixed to highest p-state.
* - cpu_perf_policy=Nominal: frequency is fixed to guaranteed HWP level or nominal p-state. * - cpu_perf_policy=Nominal: frequency is fixed to guaranteed HWP level or nominal p-state.
* The default policy is 'Performance'. * The default policy is 'Performance'.
* *
@ -317,7 +317,7 @@ void apply_frequency_policy(void)
cpuid_subleaf(0x6U, 0U, &cpuid_06_eax, &unused, &unused, &unused); cpuid_subleaf(0x6U, 0U, &cpuid_06_eax, &unused, &unused, &unused);
cpuid_subleaf(0x1U, 0U, &unused, &unused, &cpuid_01_ecx, &unused); cpuid_subleaf(0x1U, 0U, &unused, &unused, &cpuid_01_ecx, &unused);
/* Both HWP and ACPI p-state are supported. HWP is the first choise. */ /* Both HWP and ACPI p-state are supported. HWP is the first choice. */
if ((cpuid_06_eax & CPUID_EAX_HWP) != 0U) { if ((cpuid_06_eax & CPUID_EAX_HWP) != 0U) {
/* /*
* For Performance policy(default): CPU frequency will be autonomously selected between highest and lowest * For Performance policy(default): CPU frequency will be autonomously selected between highest and lowest
@ -342,7 +342,7 @@ void apply_frequency_policy(void)
pstate_req = limits->nominal_pstate; pstate_req = limits->nominal_pstate;
} }
/* PX info might be missing on some platforms (px_cnt equels 0). Do nothing if so. */ /* PX info might be missing on some platforms (px_cnt equals 0). Do nothing if so. */
if (pm_s_state_data->px_cnt != 0) { if (pm_s_state_data->px_cnt != 0) {
if (pstate_req < pm_s_state_data->px_cnt) { if (pstate_req < pm_s_state_data->px_cnt) {
msr_write(MSR_IA32_PERF_CTL, pm_s_state_data->px_data[pstate_req].control); msr_write(MSR_IA32_PERF_CTL, pm_s_state_data->px_data[pstate_req].control);