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hv: virq: refine vcpu_inject_vlapic_int() has more than one exit point

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The MISRA-C Standards suggests procedures to be single exit.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2018-12-19 23:30:50 +08:00 committed by wenlingz
parent 9c97f6bec5
commit 3bfa695565
1 changed files with 24 additions and 25 deletions
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49
hypervisor/arch/x86/virq.c
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@ -119,33 +119,32 @@ static int32_t vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
* through vmcs. * through vmcs.
*/ */
if (is_apicv_intr_delivery_supported()) { if (is_apicv_intr_delivery_supported()) {
return -1; ret = -1;
} else {
/* Query vLapic to get vector to inject */
ret = vlapic_pending_intr(vlapic, &vector);
if (ret != 0) {
/*
* From the Intel SDM, Volume 3, 6.3.2 Section "Maskable
* Hardware Interrupts":
* - maskable interrupt vectors [16,255] can be delivered
* through the local APIC.
*/
if (!(vector >= 16U && vector <= 255U)) {
dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC", vector);
ret = -1;
} else {
exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
(vector & 0xFFU));
vlapic_intr_accepted(vlapic, vector);
ret = 0;
}
}
} }
/* Query vLapic to get vector to inject */ return ret;
ret = vlapic_pending_intr(vlapic, &vector);
/*
* From the Intel SDM, Volume 3, 6.3.2 Section "Maskable
* Hardware Interrupts":
* - maskable interrupt vectors [16,255] can be delivered
* through the local APIC.
*/
if (ret == 0) {
return 0;
}
if (!(vector >= 16U && vector <= 255U)) {
dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC",
vector);
return -1;
}
exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
(vector & 0xFFU));
vlapic_intr_accepted(vlapic, vector);
return 0;
} }
static int32_t vcpu_do_pending_extint(const struct acrn_vcpu *vcpu) static int32_t vcpu_do_pending_extint(const struct acrn_vcpu *vcpu)