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hv: support CAT on hybrid platform

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On hybrid platform(e.g. ADL), there may be multiple instances of same level caches for different type of processors,
The current design only supports one global `rdt_info` for each RDT resource type.
In order to support hybrid platform, this patch introduce `rdt_ins` to represents the "instance".
Also, the number of `rdt_info` is dynamically generated by config-tool to match with physical board.

Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Tw
2022-03-28 09:35:51 +08:00
committed by acrnsi-robot
parent 19da21c898
commit 3c384a489c
4 changed files with 89 additions and 82 deletions
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14
hypervisor/arch/x86/guest/vcat.c
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@@ -24,7 +24,10 @@
*/
bool is_l2_vcat_configured(const struct acrn_vm *vm)
{
return is_vcat_configured(vm) && (get_rdt_res_cap_info(RDT_RESOURCE_L2)->num_closids > 0U);
uint16_t pcpu = ffs64(vm->hw.cpu_affinity);
const struct rdt_ins *ins = get_rdt_res_ins(RDT_RESOURCE_L2, pcpu);
return is_vcat_configured(vm) && ins != NULL && (ins->num_closids > 0U);
}
/**
@@ -32,7 +35,10 @@ bool is_l2_vcat_configured(const struct acrn_vm *vm)
*/
bool is_l3_vcat_configured(const struct acrn_vm *vm)
{
return is_vcat_configured(vm) && (get_rdt_res_cap_info(RDT_RESOURCE_L3)->num_closids > 0U);
uint16_t pcpu = ffs64(vm->hw.cpu_affinity);
const struct rdt_ins *ins = get_rdt_res_ins(RDT_RESOURCE_L3, pcpu);
return is_vcat_configured(vm) && ins != NULL && (ins->num_closids > 0U);
}
/**
@@ -175,7 +181,7 @@ static bool is_l2_vcbm_msr(const struct acrn_vm *vm, uint32_t vmsr)
/* num_vcbm_msrs = num_vclosids */
uint16_t num_vcbm_msrs = vcat_get_num_vclosids(vm);
return ((get_rdt_res_cap_info(RDT_RESOURCE_L2)->num_closids > 0U)
return (is_l2_vcat_configured(vm)
&& (vmsr >= MSR_IA32_L2_MASK_BASE) && (vmsr < (MSR_IA32_L2_MASK_BASE + num_vcbm_msrs)));
}
@@ -187,7 +193,7 @@ static bool is_l3_vcbm_msr(const struct acrn_vm *vm, uint32_t vmsr)
/* num_vcbm_msrs = num_vclosids */
uint16_t num_vcbm_msrs = vcat_get_num_vclosids(vm);
return ((get_rdt_res_cap_info(RDT_RESOURCE_L3)->num_closids > 0U)
return (is_l3_vcat_configured(vm)
&& (vmsr >= MSR_IA32_L3_MASK_BASE) && (vmsr < (MSR_IA32_L3_MASK_BASE + num_vcbm_msrs)));
}