github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-08-05 02:11:23 +00:00
Code Issues Projects Releases Wiki Activity

hv: msr: remove redundant check in write_pat_msr

Browse Source 
Reserved bits in a 8-bit PAT field has been checked in pat_mem_type_invalid.
Remove this redundant check "(PAT_FIELD_RSV_BITS & field) != 0UL" in
write_pat_msr.

Tracked-On: #1842
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This commit is contained in:
Shiqing Gao 2019-12-16 08:47:14 +08:00 committed by wenlingz
parent d4677a8917
commit 3cee259583
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/guest/vmsr.c
View File

@ -361,7 +361,7 @@ static int32_t write_pat_msr(struct acrn_vcpu *vcpu, uint64_t value)
for (i = 0U; i < 8U; i++) { for (i = 0U; i < 8U; i++) {
field = (value >> (i * 8U)) & 0xffUL; field = (value >> (i * 8U)) & 0xffUL;
if (pat_mem_type_invalid(field) || ((PAT_FIELD_RSV_BITS & field) != 0UL)) { if (is_pat_mem_type_invalid(field)) {
pr_err("invalid guest IA32_PAT: 0x%016lx", value); pr_err("invalid guest IA32_PAT: 0x%016lx", value);
ret = -EINVAL; ret = -EINVAL;
break; break;

10
hypervisor/include/arch/x86/msr.h
View File

@ -568,10 +568,13 @@
/* Miscellaneous data */ /* Miscellaneous data */
#define MSR_IA32_MISC_UNRESTRICTED_GUEST (1U<<5U) #define MSR_IA32_MISC_UNRESTRICTED_GUEST (1U<<5U)
/* 5 high-order bits in every field are reserved */
#define PAT_FIELD_RSV_BITS (0xF8UL)
#ifndef ASSEMBLER #ifndef ASSEMBLER
static inline bool pat_mem_type_invalid(uint64_t x) static inline bool is_pat_mem_type_invalid(uint64_t x)
{ {
return ((x & ~0x7UL) != 0UL || (x & 0x6UL) == 0x2UL); return (((x & PAT_FIELD_RSV_BITS) != 0UL) || ((x & 0x6UL) == 0x2UL));
} }
static inline bool is_x2apic_msr(uint32_t msr) static inline bool is_x2apic_msr(uint32_t msr)
@ -591,9 +594,6 @@ void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu);
#endif /* ASSEMBLER */ #endif /* ASSEMBLER */
/* 5 high-order bits in every field are reserved */
#define PAT_FIELD_RSV_BITS (0xF8U)
#define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \ #define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \
(PAT_MEM_TYPE_WT << 8U) + \ (PAT_MEM_TYPE_WT << 8U) + \
(PAT_MEM_TYPE_UCM << 16U) + \ (PAT_MEM_TYPE_UCM << 16U) + \