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vcpu: add get/set register APIs

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there will be 3 types of vcpu runtime contexts:
- runtime contexts always saved/restored during VM exit/entry, which
  include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and
  msr for spectre control (ia32_spec_ctrl)
- runtime contexts on-demand cached/updated during VM exit/entry, which
  include frequently used registers rsp, rip, efer, rflags, cr0 and cr4
- runtime contexts always read/write from/to VMCS, which include left
  registers not in above

this patch add get/set register APIs for vcpu runtime contexts, and unified
the save/restore method for them according to above description.

v3:
- update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4,
  use on-demand cache for reading, but always write to VMCS for writing.

v2:
- use reg_cached/reg_updated for on-demand runtime contexts
- always read/write cr3 from/to VMCS

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Jason Chen CJ
2018-07-26 14:56:47 +08:00
committed by lijinxia
parent 5aa1ad3bfc
commit 3d5d6c96ec
20 changed files with 408 additions and 325 deletions
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32
hypervisor/bsp/uefi/uefi.c
View File

@@ -54,8 +54,6 @@ void efi_spurious_handler(int vector)
int uefi_sw_loader(struct vm *vm, struct vcpu *vcpu)
{
int ret = 0;
struct run_context *cur_context =
&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
ASSERT(vm != NULL, "Incorrect argument");
@@ -67,21 +65,21 @@ int uefi_sw_loader(struct vm *vm, struct vcpu *vcpu)
vlapic_restore(vcpu->arch_vcpu.vlapic, &uefi_lapic_regs);
vcpu->entry_addr = (void *)efi_ctx->rip;
cur_context->guest_cpu_regs.regs.rax = efi_ctx->rax;
cur_context->guest_cpu_regs.regs.rbx = efi_ctx->rbx;
cur_context->guest_cpu_regs.regs.rdx = efi_ctx->rcx;
cur_context->guest_cpu_regs.regs.rcx = efi_ctx->rdx;
cur_context->guest_cpu_regs.regs.rdi = efi_ctx->rdi;
cur_context->guest_cpu_regs.regs.rsi = efi_ctx->rsi;
cur_context->guest_cpu_regs.regs.rbp = efi_ctx->rbp;
cur_context->guest_cpu_regs.regs.r8 = efi_ctx->r8;
cur_context->guest_cpu_regs.regs.r9 = efi_ctx->r9;
cur_context->guest_cpu_regs.regs.r10 = efi_ctx->r10;
cur_context->guest_cpu_regs.regs.r11 = efi_ctx->r11;
cur_context->guest_cpu_regs.regs.r12 = efi_ctx->r12;
cur_context->guest_cpu_regs.regs.r13 = efi_ctx->r13;
cur_context->guest_cpu_regs.regs.r14 = efi_ctx->r14;
cur_context->guest_cpu_regs.regs.r15 = efi_ctx->r15;
vcpu_set_gpreg(vcpu, CPU_REG_RAX, efi_ctx->rax);
vcpu_set_gpreg(vcpu, CPU_REG_RBX, efi_ctx->rbx);
vcpu_set_gpreg(vcpu, CPU_REG_RCX, efi_ctx->rcx);
vcpu_set_gpreg(vcpu, CPU_REG_RDX, efi_ctx->rdx);
vcpu_set_gpreg(vcpu, CPU_REG_RDI, efi_ctx->rdi);
vcpu_set_gpreg(vcpu, CPU_REG_RSI, efi_ctx->rsi);
vcpu_set_gpreg(vcpu, CPU_REG_RBP, efi_ctx->rbp);
vcpu_set_gpreg(vcpu, CPU_REG_R8, efi_ctx->r8);
vcpu_set_gpreg(vcpu, CPU_REG_R9, efi_ctx->r9);
vcpu_set_gpreg(vcpu, CPU_REG_R10, efi_ctx->r10);
vcpu_set_gpreg(vcpu, CPU_REG_R11, efi_ctx->r11);
vcpu_set_gpreg(vcpu, CPU_REG_R12, efi_ctx->r12);
vcpu_set_gpreg(vcpu, CPU_REG_R13, efi_ctx->r13);
vcpu_set_gpreg(vcpu, CPU_REG_R14, efi_ctx->r14);
vcpu_set_gpreg(vcpu, CPU_REG_R15, efi_ctx->r15);
/* defer irq enabling till vlapic is ready */
CPU_IRQ_ENABLE();