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https://github.com/projectacrn/acrn-hypervisor.git
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vcpu: add get/set register APIs
there will be 3 types of vcpu runtime contexts: - runtime contexts always saved/restored during VM exit/entry, which include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and msr for spectre control (ia32_spec_ctrl) - runtime contexts on-demand cached/updated during VM exit/entry, which include frequently used registers rsp, rip, efer, rflags, cr0 and cr4 - runtime contexts always read/write from/to VMCS, which include left registers not in above this patch add get/set register APIs for vcpu runtime contexts, and unified the save/restore method for them according to above description. v3: - update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4, use on-demand cache for reading, but always write to VMCS for writing. v2: - use reg_cached/reg_updated for on-demand runtime contexts - always read/write cr3 from/to VMCS Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@@ -152,6 +152,65 @@
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#ifndef ASSEMBLER
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/**
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*
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* Identifiers for architecturally defined registers.
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*
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* These register names is used in condition statement.
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* Within the following groups,register name need to be
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* kept in order:
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* General register names group (CPU_REG_RAX~CPU_REG_R15);
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* Non general register names group (CPU_REG_CR0~CPU_REG_GDTR);
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* Segement register names group (CPU_REG_ES~CPU_REG_GS).
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*/
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enum cpu_reg_name {
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/* General purpose register layout should align with
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* struct cpu_gp_regs
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*/
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CPU_REG_RAX,
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CPU_REG_RCX,
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CPU_REG_RDX,
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CPU_REG_RBX,
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CPU_REG_RSP,
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CPU_REG_RBP,
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CPU_REG_RSI,
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CPU_REG_RDI,
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CPU_REG_R8,
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CPU_REG_R9,
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CPU_REG_R10,
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CPU_REG_R11,
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CPU_REG_R12,
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CPU_REG_R13,
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CPU_REG_R14,
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CPU_REG_R15,
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CPU_REG_CR0,
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CPU_REG_CR2,
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CPU_REG_CR3,
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CPU_REG_CR4,
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CPU_REG_DR7,
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CPU_REG_RIP,
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CPU_REG_RFLAGS,
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/*CPU_REG_NATURAL_LAST*/
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CPU_REG_EFER,
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CPU_REG_PDPTE0,
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CPU_REG_PDPTE1,
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CPU_REG_PDPTE2,
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CPU_REG_PDPTE3,
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/*CPU_REG_64BIT_LAST,*/
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CPU_REG_ES,
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CPU_REG_CS,
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CPU_REG_SS,
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CPU_REG_DS,
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CPU_REG_FS,
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CPU_REG_GS,
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CPU_REG_LDTR,
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CPU_REG_TR,
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CPU_REG_IDTR,
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CPU_REG_GDTR
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/*CPU_REG_LAST*/
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};
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/**********************************/
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/* EXTERNAL VARIABLES */
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/**********************************/
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@@ -263,6 +263,8 @@ struct vcpu {
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#ifdef CONFIG_MTRR_ENABLED
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struct mtrr_state mtrr;
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#endif
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uint64_t reg_cached;
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uint64_t reg_updated;
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};
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#define is_vcpu_bsp(vcpu) ((vcpu)->vcpu_id == BOOT_CPU_ID)
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@@ -273,6 +275,25 @@ static inline void vcpu_retain_rip(struct vcpu *vcpu)
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}
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/* External Interfaces */
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uint64_t vcpu_get_gpreg(struct vcpu *vcpu, uint32_t reg);
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void vcpu_set_gpreg(struct vcpu *vcpu, uint32_t reg, uint64_t val);
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uint64_t vcpu_get_rip(struct vcpu *vcpu);
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void vcpu_set_rip(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_rsp(struct vcpu *vcpu);
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void vcpu_set_rsp(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_efer(struct vcpu *vcpu);
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void vcpu_set_efer(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_rflags(struct vcpu *vcpu);
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void vcpu_set_rflags(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_cr0(struct vcpu *vcpu);
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int vcpu_set_cr0(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_cr2(struct vcpu *vcpu);
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void vcpu_set_cr2(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_cr4(struct vcpu *vcpu);
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int vcpu_set_cr4(struct vcpu *vcpu, uint64_t val);
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uint64_t vcpu_get_pat_ext(struct vcpu *vcpu);
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void vcpu_set_pat_ext(struct vcpu *vcpu, uint64_t val);
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struct vcpu* get_ever_run_vcpu(uint16_t pcpu_id);
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int create_vcpu(uint16_t pcpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle);
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int start_vcpu(struct vcpu *vcpu);
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@@ -447,7 +447,6 @@ uint64_t vmx_rdmsr_pat(struct vcpu *vcpu);
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int vmx_wrmsr_pat(struct vcpu *vcpu, uint64_t value);
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int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0);
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int vmx_write_cr3(struct vcpu *vcpu, uint64_t cr3);
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int vmx_write_cr4(struct vcpu *vcpu, uint64_t cr4);
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static inline enum vm_cpu_mode get_vcpu_mode(struct vcpu *vcpu)
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