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hv: PTM: Create virtual root port

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Create virtual root port through add_vdev hypercall. add_vdev
identifies the virtual device to add by its vendor id and device id, then
call the corresponding function to create virtual device.

	-create_vrp(): Find the right virtual root port to create
by its secondary bus number, then initialize the virtual root port.
And finally initialize PTM related configurations.

	-destroy_vrp(): nothing to destroy

Tracked-On: #5915
Signed-off-by: Rong Liu <rong.l.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Jason Chen <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Rong Liu
2021-05-05 23:38:22 +00:00
committed by wenlingz
parent d57bf51c89
commit 3db4491e1c
5 changed files with 95 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/include/arch/x86/asm/vm_config.h
View File

@@ -153,7 +153,7 @@ struct acrn_vm_pci_dev_config {
/* TODO: All device specific attributions need move to other place */
struct target_vuart t_vuart;
uint16_t vuart_idx;
uint16_t vroot_port_idx;
uint16_t vrp_sec_bus; /* use virtual root port's secondary bus as unique identification */
uint64_t vbar_base[PCI_BAR_COUNT]; /* vbar base address of PCI device, which is power-on default value */
struct pci_pdev *pdev; /* the physical PCI device if it's a PT device */
const struct pci_vdev_ops *vdev_ops; /* operations for PCI CFG read/write */

13
hypervisor/include/dm/vroot_port.h
View File

@@ -5,14 +5,17 @@
*
*/
#ifndef __VROOT_PORT_H
#define __VROOT_PORT_H
#ifndef __VRP_H
#define __VRP_H
#include "vpci.h"
#define VROOT_PORT_VENDOR 0x8086U
#define VROOT_PORT_DEVICE 0x9d14U
#define VRP_VENDOR 0x8086U
#define VRP_DEVICE 0x9d14U
extern const struct pci_vdev_ops vroot_port_ops;
extern const struct pci_vdev_ops vrp_ops;
int32_t create_vrp(struct acrn_vm *vm, struct acrn_emul_dev *dev);
int32_t destroy_vrp(struct pci_vdev *vdev);
#endif

9
hypervisor/include/hw/pci.h
View File

@@ -120,6 +120,7 @@
#define PCI_ECAP_ID(hdr) ((uint32_t)((hdr) & 0xFFFFU))
#define PCI_ECAP_NEXT(hdr) ((uint32_t)(((hdr) >> 20U) & 0xFFCU))
#define PCIZ_SRIOV 0x10U
#define PCIZ_PTM 0x1fU
/* SRIOV Definitions */
#define PCI_SRIOV_CAP_LEN 0x40U
@@ -132,6 +133,14 @@
#define PCIR_SRIOV_VF_BAR_OFF 0x24U
#define PCIM_SRIOV_VF_ENABLE 0x1U
/* PTM Definitions */
#define PCI_PTM_CAP_LEN 0x04U
#define PCIR_PTM_CAP 0x04U
#define PCIR_PTM_CTRL 0x08U
#define PCIM_PTM_CAP_ROOT_CAPABLE 0x4U
#define PCIM_PTM_CTRL_ENABLED 0x1U
#define PCIM_PTM_CTRL_ROOT_SELECTED 0x2U
/* PCI Message Signalled Interrupts (MSI) */
#define PCIR_MSI_CTRL 0x02U
#define PCIM_MSICTRL_64BIT 0x80U