diff --git a/hypervisor/arch/x86/cpu_caps.c b/hypervisor/arch/x86/cpu_caps.c
index 2ad2ce48d..24ca0b354 100644
--- a/hypervisor/arch/x86/cpu_caps.c
+++ b/hypervisor/arch/x86/cpu_caps.c
@@ -241,6 +241,11 @@ void init_pcpu_capabilities(void)
 			&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_EDX]);
 	}
 
+	if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_INVA_TSC) {
+		cpuid(CPUID_EXTEND_INVA_TSC, &eax, &unused, &unused,
+			&boot_cpu_data.cpuid_leaves[FEAT_8000_0007_EDX]);
+	}
+
 	if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_ADDRESS_SIZE) {
 		cpuid(CPUID_EXTEND_ADDRESS_SIZE, &eax,
 			&boot_cpu_data.cpuid_leaves[FEAT_8000_0008_EBX],
@@ -366,6 +371,10 @@ int32_t detect_hardware_support(void)
 		(boot_cpu_data.virt_bits == 0U)) {
 		printf("%s, can't detect Linear/Physical Address size\n", __func__);
 		ret = -ENODEV;
+	} else if (!pcpu_has_cap(X86_FEATURE_INVA_TSC)) {
+		/* check invariant TSC */
+		printf("%s, invariant TSC not supported\n", __func__);
+		ret = -ENODEV;
 	} else if (!pcpu_has_cap(X86_FEATURE_TSC_DEADLINE)) {
 		/* lapic TSC deadline timer */
 		printf("%s, TSC deadline not supported\n", __func__);
diff --git a/hypervisor/include/arch/x86/cpu_caps.h b/hypervisor/include/arch/x86/cpu_caps.h
index 47e0aa800..513e45538 100644
--- a/hypervisor/include/arch/x86/cpu_caps.h
+++ b/hypervisor/include/arch/x86/cpu_caps.h
@@ -22,8 +22,9 @@
 #define	FEAT_7_0_EDX		4U     /* CPUID[EAX=7,ECX=0].EDX */
 #define	FEAT_8000_0001_ECX	5U     /* CPUID[8000_0001].ECX */
 #define	FEAT_8000_0001_EDX	6U     /* CPUID[8000_0001].EDX */
-#define	FEAT_8000_0008_EBX	7U     /* CPUID[8000_0008].EAX */
-#define	FEATURE_WORDS		8U
+#define	FEAT_8000_0007_EDX	7U     /* CPUID[8000_0007].EDX */
+#define	FEAT_8000_0008_EBX	8U     /* CPUID[8000_0008].EBX */
+#define	FEATURE_WORDS		9U
 
 struct cpuinfo_x86 {
 	uint8_t family, model;
diff --git a/hypervisor/include/arch/x86/cpufeatures.h b/hypervisor/include/arch/x86/cpufeatures.h
index 839bac270..dea1efc86 100644
--- a/hypervisor/include/arch/x86/cpufeatures.h
+++ b/hypervisor/include/arch/x86/cpufeatures.h
@@ -91,4 +91,7 @@
 #define X86_FEATURE_PAGE1GB	((FEAT_8000_0001_EDX << 5U) + 26U)
 #define X86_FEATURE_LM		((FEAT_8000_0001_EDX << 5U) + 29U)
 
+/* Intel-defined CPU features, CPUID level 0x80000007 (EDX)*/
+#define X86_FEATURE_INVA_TSC	((FEAT_8000_0007_EDX << 5U) + 8U)
+
 #endif /* CPUFEATURES_H */
diff --git a/hypervisor/include/arch/x86/cpuid.h b/hypervisor/include/arch/x86/cpuid.h
index eb4489140..973b1e7c9 100644
--- a/hypervisor/include/arch/x86/cpuid.h
+++ b/hypervisor/include/arch/x86/cpuid.h
@@ -119,6 +119,7 @@
 #define CPUID_EXTEND_FUNCTION_2      0x80000002U
 #define CPUID_EXTEND_FUNCTION_3      0x80000003U
 #define CPUID_EXTEND_FUNCTION_4      0x80000004U
+#define CPUID_EXTEND_INVA_TSC        0x80000007U
 #define CPUID_EXTEND_ADDRESS_SIZE    0x80000008U