mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-08-08 03:35:14 +00:00
Revert "hv: implement lowlevel S3 enter/wakeup"
This reverts commit c2be7fdedb.
This commit is contained in:
lijinxia
parent
f79ec0c8be
commit
3fcd59d3c4
@ -120,7 +120,6 @@ C_SRCS += arch/x86/trusty.c
|
|||||||
C_SRCS += arch/x86/cpu_state_tbl.c
|
C_SRCS += arch/x86/cpu_state_tbl.c
|
||||||
C_SRCS += arch/x86/mtrr.c
|
C_SRCS += arch/x86/mtrr.c
|
||||||
C_SRCS += arch/x86/pm.c
|
C_SRCS += arch/x86/pm.c
|
||||||
S_SRCS += arch/x86/wakeup.S
|
|
||||||
C_SRCS += arch/x86/guest/vcpu.c
|
C_SRCS += arch/x86/guest/vcpu.c
|
||||||
C_SRCS += arch/x86/guest/vm.c
|
C_SRCS += arch/x86/guest/vm.c
|
||||||
C_SRCS += arch/x86/guest/instr_emul_wrapper.c
|
C_SRCS += arch/x86/guest/instr_emul_wrapper.c
|
||||||
|
|||||||
@ -4,8 +4,6 @@
|
|||||||
*/
|
*/
|
||||||
#include <hypervisor.h>
|
#include <hypervisor.h>
|
||||||
|
|
||||||
struct run_context cpu_ctx;
|
|
||||||
|
|
||||||
void restore_msrs(void)
|
void restore_msrs(void)
|
||||||
{
|
{
|
||||||
#ifdef STACK_PROTECTOR
|
#ifdef STACK_PROTECTOR
|
||||||
|
|||||||
@ -1,96 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) <2018> Intel Corporation
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#include <vcpu.h>
|
|
||||||
|
|
||||||
.text
|
|
||||||
.align 8
|
|
||||||
.code64
|
|
||||||
.extern restore_msrs
|
|
||||||
.extern cpu_ctx
|
|
||||||
.extern load_gdtr_and_tr
|
|
||||||
|
|
||||||
.global __enter_s3
|
|
||||||
__enter_s3:
|
|
||||||
movq %rax, CPU_CONTEXT_OFFSET_RAX + cpu_ctx(%rip)
|
|
||||||
movq %rbx, CPU_CONTEXT_OFFSET_RBX + cpu_ctx(%rip)
|
|
||||||
movq %rcx, CPU_CONTEXT_OFFSET_RCX + cpu_ctx(%rip)
|
|
||||||
movq %rdx, CPU_CONTEXT_OFFSET_RDX + cpu_ctx(%rip)
|
|
||||||
movq %rdi, CPU_CONTEXT_OFFSET_RDI + cpu_ctx(%rip)
|
|
||||||
movq %rsi, CPU_CONTEXT_OFFSET_RSI + cpu_ctx(%rip)
|
|
||||||
movq %rbp, CPU_CONTEXT_OFFSET_RBP + cpu_ctx(%rip)
|
|
||||||
movq %rsp, CPU_CONTEXT_OFFSET_RSP + cpu_ctx(%rip)
|
|
||||||
movq %r8, CPU_CONTEXT_OFFSET_R8 + cpu_ctx(%rip)
|
|
||||||
movq %r9, CPU_CONTEXT_OFFSET_R9 + cpu_ctx(%rip)
|
|
||||||
movq %r10, CPU_CONTEXT_OFFSET_R10 + cpu_ctx(%rip)
|
|
||||||
movq %r11, CPU_CONTEXT_OFFSET_R11 + cpu_ctx(%rip)
|
|
||||||
movq %r12, CPU_CONTEXT_OFFSET_R12 + cpu_ctx(%rip)
|
|
||||||
movq %r13, CPU_CONTEXT_OFFSET_R13 + cpu_ctx(%rip)
|
|
||||||
movq %r14, CPU_CONTEXT_OFFSET_R14 + cpu_ctx(%rip)
|
|
||||||
movq %r15, CPU_CONTEXT_OFFSET_R15 + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
pushfq
|
|
||||||
popq CPU_CONTEXT_OFFSET_RFLAGS + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
sidt CPU_CONTEXT_OFFSET_IDTR + cpu_ctx(%rip)
|
|
||||||
sldt CPU_CONTEXT_OFFSET_LDTR + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
mov %cr0, %rax
|
|
||||||
mov %rax, CPU_CONTEXT_OFFSET_CR0 + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
mov %cr3, %rax
|
|
||||||
mov %rax, CPU_CONTEXT_OFFSET_CR3 + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
mov %cr4, %rax
|
|
||||||
mov %rax, CPU_CONTEXT_OFFSET_CR4 + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
wbinvd
|
|
||||||
|
|
||||||
/* Will add the function call to enter Sx here*/
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* When system resume from S3, trampoline_start64 will
|
|
||||||
* jump to restore_s3_context after setup temporary stack.
|
|
||||||
*/
|
|
||||||
.global restore_s3_context
|
|
||||||
restore_s3_context:
|
|
||||||
mov CPU_CONTEXT_OFFSET_CR4 + cpu_ctx(%rip), %rax
|
|
||||||
mov %rax, %cr4
|
|
||||||
|
|
||||||
mov CPU_CONTEXT_OFFSET_CR3 + cpu_ctx(%rip), %rax
|
|
||||||
mov %rax, %cr3
|
|
||||||
|
|
||||||
mov CPU_CONTEXT_OFFSET_CR0 + cpu_ctx(%rip), %rax
|
|
||||||
mov %rax, %cr0
|
|
||||||
|
|
||||||
lidt CPU_CONTEXT_OFFSET_IDTR + cpu_ctx(%rip)
|
|
||||||
lldt CPU_CONTEXT_OFFSET_LDTR + cpu_ctx(%rip)
|
|
||||||
|
|
||||||
mov CPU_CONTEXT_OFFSET_SS + cpu_ctx(%rip), %ss
|
|
||||||
mov CPU_CONTEXT_OFFSET_RSP + cpu_ctx(%rip), %rsp
|
|
||||||
|
|
||||||
pushq CPU_CONTEXT_OFFSET_RFLAGS + cpu_ctx(%rip)
|
|
||||||
popfq
|
|
||||||
|
|
||||||
call load_gdtr_and_tr
|
|
||||||
call restore_msrs
|
|
||||||
|
|
||||||
movq CPU_CONTEXT_OFFSET_RAX + cpu_ctx(%rip), %rax
|
|
||||||
movq CPU_CONTEXT_OFFSET_RBX + cpu_ctx(%rip), %rbx
|
|
||||||
movq CPU_CONTEXT_OFFSET_RCX + cpu_ctx(%rip), %rcx
|
|
||||||
movq CPU_CONTEXT_OFFSET_RDX + cpu_ctx(%rip), %rdx
|
|
||||||
movq CPU_CONTEXT_OFFSET_RDI + cpu_ctx(%rip), %rdi
|
|
||||||
movq CPU_CONTEXT_OFFSET_RSI + cpu_ctx(%rip), %rsi
|
|
||||||
movq CPU_CONTEXT_OFFSET_RBP + cpu_ctx(%rip), %rbp
|
|
||||||
movq CPU_CONTEXT_OFFSET_R8 + cpu_ctx(%rip), %r8
|
|
||||||
movq CPU_CONTEXT_OFFSET_R9 + cpu_ctx(%rip), %r9
|
|
||||||
movq CPU_CONTEXT_OFFSET_R10 + cpu_ctx(%rip), %r10
|
|
||||||
movq CPU_CONTEXT_OFFSET_R11 + cpu_ctx(%rip), %r11
|
|
||||||
movq CPU_CONTEXT_OFFSET_R12 + cpu_ctx(%rip), %r12
|
|
||||||
movq CPU_CONTEXT_OFFSET_R13 + cpu_ctx(%rip), %r13
|
|
||||||
movq CPU_CONTEXT_OFFSET_R14 + cpu_ctx(%rip), %r14
|
|
||||||
movq CPU_CONTEXT_OFFSET_R15 + cpu_ctx(%rip), %r15
|
|
||||||
|
|
||||||
retq
|
|
||||||
@ -1,12 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) <2018> Intel Corporation
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef HOST_PM_H
|
|
||||||
|
|
||||||
extern void __enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
|
|
||||||
uint32_t pm1b_cnt_val);
|
|
||||||
extern void restore_s3_context(void);
|
|
||||||
|
|
||||||
#endif /* ARCH_X86_PM_H */
|
|
||||||
@ -19,7 +19,6 @@
|
|||||||
#include <vcpu.h>
|
#include <vcpu.h>
|
||||||
#include <trusty.h>
|
#include <trusty.h>
|
||||||
#include <guest_pm.h>
|
#include <guest_pm.h>
|
||||||
#include <host_pm.h>
|
|
||||||
#include <vm.h>
|
#include <vm.h>
|
||||||
#include <cpuid.h>
|
#include <cpuid.h>
|
||||||
#include <mmu.h>
|
#include <mmu.h>
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user