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hv: Support WAITPKG instructions in guest VM

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TPAUSE, UMONITOR or UMWAIT instructions execution in guest VM cause
a #UD if "enable user wait and pause" (bit 26) of VMX_PROCBASED_CTLS2
is not set. To fix this issue, set the bit 26 of VMX_PROCBASED_CTLS2.

Besides, these WAITPKG instructions uses MSR_IA32_UMWAIT_CONTROL. So
load corresponding vMSR value during context switch in of a vCPU.

Please note, the TPAUSE or UMWAIT instruction causes a VM exit if the
"RDTSC exiting" and "enable user wait and pause" are both 1. In ACRN
hypervisor, "RDTSC exiting" is always 0. So TPAUSE or UMWAIT doesn't
cause a VM exit.

Performance impact:
    MSR_IA32_UMWAIT_CONTROL read costs ~19 cycles;
    MSR_IA32_UMWAIT_CONTROL write costs ~63 cycles.

Tracked-On: #6006
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
This commit is contained in:
Shuo A Liu
2021-05-11 18:54:14 +08:00
committed by wenlingz
parent ebadf00de8
commit 3fffa68665
7 changed files with 36 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
hypervisor/include/arch/x86/asm/cpufeatures.h
View File

@@ -80,6 +80,7 @@
#define X86_FEATURE_CLFLUSHOPT ((FEAT_7_0_EBX << 5U) + 23U)
/* Intel-defined CPU features, CPUID level 0x00000007 (ECX)*/
#define X86_FEATURE_WAITPKG ((FEAT_7_0_ECX << 5U) + 5U)
#define X86_FEATURE_KEYLOCKER ((FEAT_7_0_ECX << 5U) + 23U)
/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/

2
hypervisor/include/arch/x86/asm/guest/vcpu.h
View File

@@ -171,7 +171,7 @@ enum reset_mode;
#define SECURE_WORLD 1
#define NUM_WORLD_MSRS 2U
#define NUM_COMMON_MSRS 21U
#define NUM_COMMON_MSRS 22U
#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS)
#define EOI_EXIT_BITMAP_SIZE 256U

1
hypervisor/include/arch/x86/asm/msr.h
View File

@@ -42,6 +42,7 @@
#define MSR_IA32_PMC6 0x000000C7U
#define MSR_IA32_PMC7 0x000000C8U
#define MSR_IA32_CORE_CAPABILITIES 0x000000CFU
#define MSR_IA32_UMWAIT_CONTROL 0x000000E1U
/* Max. qualified performance clock counter */
#define MSR_IA32_MPERF 0x000000E7U
/* Actual performance clock counter */

1
hypervisor/include/arch/x86/asm/vmx.h
View File

@@ -317,6 +317,7 @@
#define VMX_PROCBASED_CTLS2_RDSEED (1U<<16U)
#define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18U)
#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20U)
#define VMX_PROCBASED_CTLS2_UWAIT_PAUSE (1U<<26U)
#define VMX_PROCBASED_CTLS3_LOADIWKEY (1U<<0U)
/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */