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HV: pm: cleanup for misra integral type violations

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The patch fixes integral type related violations on HV pm part.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Victor Sun 2018-07-11 10:49:04 +08:00 committed by Jack Ren
parent 202bc541b6
commit 401ffd1e39
3 changed files with 37 additions and 33 deletions
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34
hypervisor/arch/x86/guest/pm.c
View File

@ -36,7 +36,7 @@ static void vm_setup_cpu_px(struct vm *vm)
uint32_t px_data_size;
vm->pm.px_cnt = 0U;
(void)memset(vm->pm.px_data, 0,
(void)memset(vm->pm.px_data, 0U,
MAX_PSTATE * sizeof(struct cpu_px_data));
if ((boot_cpu_data.state_info.px_cnt == 0U)
@ -49,7 +49,7 @@ static void vm_setup_cpu_px(struct vm *vm)
vm->pm.px_cnt = boot_cpu_data.state_info.px_cnt;
px_data_size = vm->pm.px_cnt * sizeof(struct cpu_px_data);
px_data_size = ((uint32_t)vm->pm.px_cnt) * sizeof(struct cpu_px_data);
(void)memcpy_s(vm->pm.px_data, px_data_size,
boot_cpu_data.state_info.px_data, px_data_size);
@ -61,7 +61,7 @@ static void vm_setup_cpu_cx(struct vm *vm)
uint32_t cx_data_size;
vm->pm.cx_cnt = 0U;
(void)memset(vm->pm.cx_data, 0,
(void)memset(vm->pm.cx_data, 0U,
MAX_CSTATE * sizeof(struct cpu_cx_data));
if ((boot_cpu_data.state_info.cx_cnt == 0U)
@ -74,7 +74,7 @@ static void vm_setup_cpu_cx(struct vm *vm)
vm->pm.cx_cnt = boot_cpu_data.state_info.cx_cnt;
cx_data_size = vm->pm.cx_cnt * sizeof(struct cpu_cx_data);
cx_data_size = ((uint32_t)vm->pm.cx_cnt) * sizeof(struct cpu_cx_data);
/* please note pm.cx_data[0] is a empty space holder,
* pm.cx_data[1...MAX_CX_ENTRY] would be used to store cx entry datas.
@ -88,13 +88,13 @@ static inline void init_cx_port(struct vm *vm)
{
uint8_t cx_idx;
for (cx_idx = 2; cx_idx <= vm->pm.cx_cnt; cx_idx++) {
for (cx_idx = 2U; cx_idx <= vm->pm.cx_cnt; cx_idx++) {
struct cpu_cx_data *cx_data = vm->pm.cx_data + cx_idx;
if (cx_data->cx_reg.space_id == SPACE_SYSTEM_IO) {
uint16_t port = (uint16_t)cx_data->cx_reg.address;
allow_guest_io_access(vm, port, 1);
allow_guest_io_access(vm, port, 1U);
}
}
}
@ -124,14 +124,14 @@ int vm_load_pm_s_state(struct vm *vm)
}
}
static inline uint16_t s3_enabled(uint16_t pm1_cnt)
static inline uint32_t s3_enabled(uint32_t pm1_cnt)
{
return pm1_cnt & (1 << BIT_SLP_EN);
return pm1_cnt & (1U << BIT_SLP_EN);
}
static inline uint8_t get_slp_typx(uint16_t pm1_cnt)
static inline uint8_t get_slp_typx(uint32_t pm1_cnt)
{
return (pm1_cnt & 0x1fff) >> BIT_SLP_TYPx;
return (uint8_t)((pm1_cnt & 0x1fffU) >> BIT_SLP_TYPx);
}
static uint32_t pm1ab_io_read(__unused struct vm_io_handler *hdlr,
@ -166,7 +166,7 @@ static void pm1ab_io_write(__unused struct vm_io_handler *hdlr,
if (vm->pm.sx_state_data->pm1b_cnt.address) {
pm1a_cnt_ready = v;
} else {
enter_s3(vm, v, 0);
enter_s3(vm, v, 0U);
}
return;
}
@ -201,7 +201,7 @@ void register_gas_io_handler(struct vm *vm, struct acpi_generic_address *gas)
return;
gas_io.flags = IO_ATTR_RW,
gas_io.base = gas->address,
gas_io.base = (uint16_t)gas->address,
gas_io.len = io_len[gas->access_size];
register_io_emulation_handler(vm, &gas_io,
@ -213,8 +213,10 @@ void register_gas_io_handler(struct vm *vm, struct acpi_generic_address *gas)
void register_pm1ab_handler(struct vm *vm)
{
register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1a_evt);
register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1b_evt);
register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1a_cnt);
register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1b_cnt);
struct pm_s_state_data *sx_data = vm->pm.sx_state_data;
register_gas_io_handler(vm, &(sx_data->pm1a_evt));
register_gas_io_handler(vm, &(sx_data->pm1b_evt));
register_gas_io_handler(vm, &(sx_data->pm1a_cnt));
register_gas_io_handler(vm, &(sx_data->pm1b_cnt));
}

30
hypervisor/arch/x86/pm.c
View File

@ -26,17 +26,17 @@ static void acpi_gas_write(struct acpi_generic_address *gas, uint32_t val)
if (gas->space_id == SPACE_SYSTEM_MEMORY)
mmio_write_word(val16, HPA2HVA(gas->address));
else
io_write_word(val16, gas->address);
io_write_word(val16, (uint16_t)gas->address);
}
static uint32_t acpi_gas_read(struct acpi_generic_address *gas)
{
uint32_t ret = 0;
uint32_t ret = 0U;
if (gas->space_id == SPACE_SYSTEM_MEMORY)
ret = mmio_read_word(HPA2HVA(gas->address));
else
ret = io_read_word(gas->address);
ret = io_read_word((uint16_t)gas->address);
return ret;
}
@ -45,22 +45,24 @@ void do_acpi_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val)
{
uint32_t s1, s2;
struct pm_s_state_data *sx_data = vm->pm.sx_state_data;
acpi_gas_write(&vm->pm.sx_state_data->pm1a_cnt, pm1a_cnt_val);
acpi_gas_write(&(sx_data->pm1a_cnt), pm1a_cnt_val);
if (vm->pm.sx_state_data->pm1b_cnt.address != 0)
acpi_gas_write(&vm->pm.sx_state_data->pm1b_cnt, pm1b_cnt_val);
if (vm->pm.sx_state_data->pm1b_cnt.address != 0U)
acpi_gas_write(&(sx_data->pm1b_cnt), pm1b_cnt_val);
while (1) {
/* polling PM1 state register to detect wether
* the Sx state enter is interrupted by wakeup event.
*/
s1 = s2 = 0;
s1 = 0U;
s2 = 0U;
s1 = acpi_gas_read(&vm->pm.sx_state_data->pm1a_evt);
s1 = acpi_gas_read(&(sx_data->pm1a_evt));
if (vm->pm.sx_state_data->pm1b_evt.address != 0) {
s2 = acpi_gas_read(&vm->pm.sx_state_data->pm1b_evt);
if (vm->pm.sx_state_data->pm1b_evt.address != 0U) {
s2 = acpi_gas_read(&(sx_data->pm1b_evt));
s1 |= s2;
}
@ -68,7 +70,7 @@ void do_acpi_s3(struct vm *vm, uint32_t pm1a_cnt_val,
* WAK_STS(bit 15) is set if system will transition to working
* state.
*/
if ((s1 & (1 << BIT_WAK_STS)) != 0)
if ((s1 & (1U << BIT_WAK_STS)) != 0U)
break;
}
}
@ -76,15 +78,15 @@ void do_acpi_s3(struct vm *vm, uint32_t pm1a_cnt_val,
int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val)
{
uint32_t pcpu_id;
uint64_t pmain_entry_saved;
uint32_t guest_wakeup_vec32;
uint16_t pcpu_id;
/* We assume enter s3 success by default */
host_enter_s3_success = 1;
host_enter_s3_success = 1U;
if (vm->pm.sx_state_data == NULL) {
pr_err("No Sx state info avaiable. No Sx support");
host_enter_s3_success = 0;
host_enter_s3_success = 0U;
return -1;
}

6
hypervisor/include/arch/x86/io.h
View File

@ -140,9 +140,9 @@ struct vm_io_handler {
struct vm_io_handler_desc desc;
};
#define IO_ATTR_R 0
#define IO_ATTR_RW 1
#define IO_ATTR_NO_ACCESS 2
#define IO_ATTR_R 0U
#define IO_ATTR_RW 1U
#define IO_ATTR_NO_ACCESS 2U
/* External Interfaces */
int io_instr_vmexit_handler(struct vcpu *vcpu);