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hv: microcode: Enable microcode update from SOS.

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microcode update from UOS is disabled.
microcode version checking is available for both SOS and UOS.

There are two TODOs of this patch:
1. This patch only update the uCode on pCPUs SOS owned. For the
   pCPUs not owned by SOS, the uCode is not updated. To handle
   this gap, we will have SOS own all pCPUs at boot time. So
   all pCPUs could have uCode updated. This will be handled
   in the patch to enable SOS own all pCPUs at boot time.

2. gva2gpa now doesn't check possible page table walk failure.
   Will add the failure check in gva2gpa in different patch.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Anthony Xu (anthony.xu@intel.com)
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
This commit is contained in:
Yin Fengwei
2018-03-06 21:22:30 +08:00
committed by Jack Ren
parent 4110e25eae
commit 4073b37369
6 changed files with 172 additions and 1 deletions
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22
hypervisor/arch/x86/guest/vmsr.c
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@@ -32,10 +32,14 @@
#include <acrn_common.h>
#include <hv_arch.h>
#include <hv_debug.h>
#include <ucode.h>
/*MRS need to be emulated, the order in this array better as freq of ops*/
static const uint32_t emulated_msrs[] = {
MSR_IA32_TSC_DEADLINE, /* Enable TSC_DEADLINE VMEXIT */
MSR_IA32_BIOS_UPDT_TRIG, /* Enable MSR_IA32_BIOS_UPDT_TRIG */
MSR_IA32_BIOS_SIGN_ID, /* Enable MSR_IA32_BIOS_SIGN_ID */
/* following MSR not emulated now */
/*
@@ -51,6 +55,8 @@ static const uint32_t emulated_msrs[] = {
/* the index is matched with emulated msrs array*/
enum {
IDX_TSC_DEADLINE,
IDX_BIOS_UPDT_TRIG,
IDX_BIOS_SIGN_ID,
IDX_MAX_MSR
};
@@ -185,6 +191,11 @@ int rdmsr_handler(struct vcpu *vcpu)
vcpu_inject_gp(vcpu);
break;
}
case MSR_IA32_BIOS_SIGN_ID:
{
v = get_microcode_version();
break;
}
/* following MSR not emulated now just left for future */
case MSR_IA32_SYSENTER_CS:
@@ -273,6 +284,17 @@ int wrmsr_handler(struct vcpu *vcpu)
vcpu_inject_gp(vcpu);
break;
}
case MSR_IA32_BIOS_SIGN_ID:
{
break;
}
case MSR_IA32_BIOS_UPDT_TRIG:
{
/* We only allow SOS to do uCode update */
if (is_vm0(vcpu->vm))
acrn_update_ucode(vcpu, v);
break;
}
/* following MSR not emulated now just left for future */
case MSR_IA32_SYSENTER_CS: