github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-09-28 03:56:14 +00:00
Code Issues Projects Releases Wiki Activity

hv: vpci: add _v prefix for some function name

Browse Source 
Add _v prefix for some function name to indicate this function wants to operate
on virtual CFG space or virtual BAR register.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
2020-03-09 13:05:09 +08:00
committed by Xie, Nanlin
parent 835dc22a18
commit 41350c533c
8 changed files with 86 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

76
hypervisor/dm/vpci/vhostbridge.c
View File

@@ -47,45 +47,45 @@
static void init_vhostbridge(struct pci_vdev *vdev)
{
/* PCI config space */
pci_vdev_write_cfg(vdev, PCIR_VENDOR, 2U, 0x8086U);
pci_vdev_write_cfg(vdev, PCIR_DEVICE, 2U, 0x5af0U);
pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, 0x8086U);
pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, 0x5af0U);
pci_vdev_write_cfg(vdev, PCIR_REVID, 1U, 0xbU);
pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0xbU);
pci_vdev_write_cfg(vdev, PCIR_HDRTYPE, 1U, (PCIM_HDRTYPE_NORMAL | PCIM_MFDEV));
pci_vdev_write_cfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
pci_vdev_write_cfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_HOST);
pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, (PCIM_HDRTYPE_NORMAL | PCIM_MFDEV));
pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_HOST);
pci_vdev_write_cfg(vdev, 0x34U, 1U, 0xe0U);
pci_vdev_write_cfg(vdev, 0x3cU, 1U, 0xe0U);
pci_vdev_write_cfg(vdev, 0x48U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0x4aU, 1U, 0xd1U);
pci_vdev_write_cfg(vdev, 0x4bU, 1U, 0xfeU);
pci_vdev_write_cfg(vdev, 0x50U, 1U, 0xc1U);
pci_vdev_write_cfg(vdev, 0x51U, 1U, 0x2U);
pci_vdev_write_cfg(vdev, 0x54U, 1U, 0x33U);
pci_vdev_write_cfg(vdev, 0x58U, 1U, 0x7U);
pci_vdev_write_cfg(vdev, 0x5aU, 1U, 0xf0U);
pci_vdev_write_cfg(vdev, 0x5bU, 1U, 0x7fU);
pci_vdev_write_cfg(vdev, 0x60U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0x63U, 1U, 0xe0U);
pci_vdev_write_cfg(vdev, 0xabU, 1U, 0x80U);
pci_vdev_write_cfg(vdev, 0xacU, 1U, 0x2U);
pci_vdev_write_cfg(vdev, 0xb0U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0xb3U, 1U, 0x7cU);
pci_vdev_write_cfg(vdev, 0xb4U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0xb6U, 1U, 0x80U);
pci_vdev_write_cfg(vdev, 0xb7U, 1U, 0x7bU);
pci_vdev_write_cfg(vdev, 0xb8U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0xbbU, 1U, 0x7bU);
pci_vdev_write_cfg(vdev, 0xbcU, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0xbfU, 1U, 0x80U);
pci_vdev_write_cfg(vdev, 0xe0U, 1U, 0x9U);
pci_vdev_write_cfg(vdev, 0xe2U, 1U, 0xcU);
pci_vdev_write_cfg(vdev, 0xe3U, 1U, 0x1U);
pci_vdev_write_cfg(vdev, 0xf5U, 1U, 0xfU);
pci_vdev_write_cfg(vdev, 0xf6U, 1U, 0x1cU);
pci_vdev_write_cfg(vdev, 0xf7U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0x34U, 1U, 0xe0U);
pci_vdev_write_vcfg(vdev, 0x3cU, 1U, 0xe0U);
pci_vdev_write_vcfg(vdev, 0x48U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0x4aU, 1U, 0xd1U);
pci_vdev_write_vcfg(vdev, 0x4bU, 1U, 0xfeU);
pci_vdev_write_vcfg(vdev, 0x50U, 1U, 0xc1U);
pci_vdev_write_vcfg(vdev, 0x51U, 1U, 0x2U);
pci_vdev_write_vcfg(vdev, 0x54U, 1U, 0x33U);
pci_vdev_write_vcfg(vdev, 0x58U, 1U, 0x7U);
pci_vdev_write_vcfg(vdev, 0x5aU, 1U, 0xf0U);
pci_vdev_write_vcfg(vdev, 0x5bU, 1U, 0x7fU);
pci_vdev_write_vcfg(vdev, 0x60U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0x63U, 1U, 0xe0U);
pci_vdev_write_vcfg(vdev, 0xabU, 1U, 0x80U);
pci_vdev_write_vcfg(vdev, 0xacU, 1U, 0x2U);
pci_vdev_write_vcfg(vdev, 0xb0U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0xb3U, 1U, 0x7cU);
pci_vdev_write_vcfg(vdev, 0xb4U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0xb6U, 1U, 0x80U);
pci_vdev_write_vcfg(vdev, 0xb7U, 1U, 0x7bU);
pci_vdev_write_vcfg(vdev, 0xb8U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0xbbU, 1U, 0x7bU);
pci_vdev_write_vcfg(vdev, 0xbcU, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0xbfU, 1U, 0x80U);
pci_vdev_write_vcfg(vdev, 0xe0U, 1U, 0x9U);
pci_vdev_write_vcfg(vdev, 0xe2U, 1U, 0xcU);
pci_vdev_write_vcfg(vdev, 0xe3U, 1U, 0x1U);
pci_vdev_write_vcfg(vdev, 0xf5U, 1U, 0xfU);
pci_vdev_write_vcfg(vdev, 0xf6U, 1U, 0x1cU);
pci_vdev_write_vcfg(vdev, 0xf7U, 1U, 0x1U);
}
static void deinit_vhostbridge(__unused struct pci_vdev *vdev)
@@ -101,7 +101,7 @@ static void deinit_vhostbridge(__unused struct pci_vdev *vdev)
static int32_t read_vhostbridge_cfg(const struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val)
{
*val = pci_vdev_read_cfg(vdev, offset, bytes);
*val = pci_vdev_read_vcfg(vdev, offset, bytes);
return 0;
}
@@ -115,7 +115,7 @@ static int32_t write_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
if (!is_bar_offset(PCI_BAR_COUNT, offset)) {
pci_vdev_write_cfg(vdev, offset, bytes, val);
pci_vdev_write_vcfg(vdev, offset, bytes, val);
}
return 0;
}