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config-tools: extract the SSRAM area size
The GPA SSRAM area size in pre-launched VMs was hard-coded to 8MB. Since this area is mapped from host SSRAM area, it will cause compile problem when host's SSRAM area is larger than 8MB. To solve this issue, we have to calculate SSRAM area's size in gpa.py, and generate a macro PRE_RTVM_SW_SRAM_MAX_SIZE for HV to use. PRE_RTVM_SW_SRAM_START_GPA/END_GPA can be calculated by end/size in HV, so they are removed. When SSRAM is not configured in the system, PRE_RTVM_SW_SRAM_MAX_SIZE is set to 0. Crl_bin is not needed in guest. So it's size is removed in bin_gen.py. Tracked-On: #7212 Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
This commit is contained in:
Zhou, Wu
acrnsi-robot
parent
5011b9396d
commit
423312881d
@ -26,10 +26,8 @@ def move_rtct_ssram_and_bin_entries(rtct, new_base_addr, new_area_max_size):
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'''
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if rtct.version == 1:
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expect_ssram_type = acpiparser.rtct.ACPI_RTCT_V1_TYPE_SoftwareSRAM
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expect_bin_type = acpiparser.rtct.ACPI_RTCT_V1_TYPE_CRL_Binary
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elif rtct.version == 2:
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expect_ssram_type = acpiparser.rtct.ACPI_RTCT_V2_TYPE_SoftwareSRAM
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expect_bin_type = acpiparser.rtct.ACPI_RTCT_V2_TYPE_CRL_Binary
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else:
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raise Exception("RTCT version error! ", rtct.version)
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top = 0
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@ -38,17 +36,12 @@ def move_rtct_ssram_and_bin_entries(rtct, new_base_addr, new_area_max_size):
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if entry.type == expect_ssram_type:
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top = (entry.base + entry.size) if top < (entry.base + entry.size) else top
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base = entry.base if base == 0 or entry.base < base else base
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elif entry.type == expect_bin_type:
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top = (entry.address + entry.size) if top < (entry.address + entry.size) else top
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base = entry.address if base == 0 or entry.address < base else base
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if new_area_max_size < (top - base):
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raise Exception("not enough space in guest VE820 SSRAM area!")
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rtct_move_offset = new_base_addr - base
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for entry in rtct.entries:
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if entry.type == expect_ssram_type:
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entry.base += rtct_move_offset
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elif entry.type == expect_bin_type:
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entry.address += rtct_move_offset
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# re-calculate checksum
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rtct.header.checksum = 0
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rtct.header.checksum = 0 - sum(bytes(rtct))
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@ -7,7 +7,7 @@
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import sys, os, re
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sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', 'library'))
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import common, lib.error, lib.lib
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import common, lib.error, lib.lib, math
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from collections import namedtuple
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# VMSIX devices list
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@ -72,14 +72,13 @@ VMSIX_VBAR_SIZE = 4 * SIZE_K
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# Constant for VIRT_ACPI_NVS_ADDR
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"""
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VIRT_ACPI_NVS_ADDR, PRE_RTVM_SW_SRAM_BASE_GPA and PRE_RTVM_SW_SRAM_MAX_SIZE
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VIRT_ACPI_NVS_ADDR and PRE_RTVM_SW_SRAM_END_GPA
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need to be consistant with the layout of hypervisor\arch\x86\guest\ve820.c
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"""
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VIRT_ACPI_NVS_ADDR = 0x7FF00000
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RESERVED_NVS_AREA = 0xB0000
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PRE_RTVM_SW_SRAM_BASE_GPA = 0x7F5FB000
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PRE_RTVM_SW_SRAM_MAX_SIZE = 0x800000
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PRE_RTVM_SW_SRAM_END_GPA = (0x7FDFB000 - 1)
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class AddrWindow(namedtuple(
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"AddrWindow", [
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@ -470,6 +469,7 @@ def allocate_io_port(board_etree, scenario_etree, allocation_etree):
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def allocate_ssram_region(board_etree, scenario_etree, allocation_etree):
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# Guest physical address of the SW SRAM allocated to a pre-launched VM
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ssram_area_max_size = 0
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enabled = common.get_node("//SSRAM_ENABLED/text()", scenario_etree)
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if enabled == "y":
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pre_rt_vms = common.get_node("//vm[load_order = 'PRE_LAUNCHED_VM' and vm_type = 'RTVM']", scenario_etree)
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@ -477,15 +477,22 @@ def allocate_ssram_region(board_etree, scenario_etree, allocation_etree):
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vm_id = pre_rt_vms.get("id")
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l3_sw_sram = board_etree.xpath("//cache[@level='3']/capability[@id='Software SRAM']")
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if l3_sw_sram:
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start = min(map(lambda x: int(x.find("start").text, 16), l3_sw_sram))
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end = max(map(lambda x: int(x.find("end").text, 16), l3_sw_sram))
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# Calculate SSRAM area size. Containing all cache parts
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top = 0
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base = 0
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for ssram in board_etree.xpath("//cache/capability[@id='Software SRAM']"):
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entry_base = int(common.get_node("./start/text()", ssram), 16)
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entry_size = int(common.get_node("./size/text()", ssram))
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top = (entry_base + entry_size) if top < (entry_base + entry_size) else top
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base = entry_base if base == 0 or entry_base < base else base
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ssram_area_max_size = math.ceil((top - base)/0x1000) * 0x1000
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allocation_vm_node = common.get_node(f"/acrn-config/vm[@id = '{vm_id}']", allocation_etree)
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if allocation_vm_node is None:
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allocation_vm_node = common.append_node("/acrn-config/vm", None, allocation_etree, id = vm_id)
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common.append_node("./ssram/start_gpa", hex(PRE_RTVM_SW_SRAM_BASE_GPA), allocation_vm_node)
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common.append_node("./ssram/end_gpa", hex(PRE_RTVM_SW_SRAM_BASE_GPA + (end - start)), allocation_vm_node)
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common.append_node("./ssram/max_size", hex(PRE_RTVM_SW_SRAM_MAX_SIZE), allocation_vm_node)
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common.append_node("./ssram/start_gpa", hex(PRE_RTVM_SW_SRAM_END_GPA - ssram_area_max_size + 1), allocation_vm_node)
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common.append_node("./ssram/end_gpa", hex(PRE_RTVM_SW_SRAM_END_GPA), allocation_vm_node)
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common.append_node("./ssram/max_size", str(ssram_area_max_size), allocation_vm_node)
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def allocate_log_area(board_etree, scenario_etree, allocation_etree):
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tpm2_enabled = common.get_node(f"//vm[@id = '0']/mmio_resources/TPM2/text()", scenario_etree)
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@ -523,7 +530,10 @@ def pt_dev_io_port_passthrough(board_etree, scenario_etree, allocation_etree):
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... ...
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| TPM2 log area at 0x7FFB0000 |
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... ...
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| SSRAM area at 0x7F5FB000 |
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+--------------------------------------------------+ <--End of SSRAM area, at Offset 0x7FDFB000
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| SSRAM area |
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+--------------------------------------------------+ <--Start of SSRAM area
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| | (Depends on the host SSRAM area size)
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... ...
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| |
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+--------------------------------------------------+ <--Offset 0
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@ -24,7 +24,7 @@
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<xsl:apply-templates select="board-data/acrn-config" />
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<xsl:apply-templates select="config-data/acrn-config" />
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<xsl:apply-templates select="allocation-data//ssram" />
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<xsl:apply-templates select="allocation-data/acrn-config" />
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<xsl:value-of select="acrn:include-guard-end('MISC_CFG_H')" />
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</xsl:template>
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@ -44,10 +44,15 @@
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<xsl:call-template name="vm_boot_args" />
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</xsl:template>
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<xsl:template match="allocation-data//ssram">
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<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_ENABLED', 1, '')" />
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<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_BASE_GPA', start_gpa, 'UL')" />
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<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_END_GPA', end_gpa, 'UL')" />
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<xsl:template match="allocation-data/acrn-config">
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<xsl:choose>
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<xsl:when test="//ssram">
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<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_MAX_SIZE', //ssram/max_size, 'UL')" />
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</xsl:when>
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<xsl:otherwise>
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<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_MAX_SIZE', 0, 'UL')" />
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</xsl:otherwise>
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</xsl:choose>
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</xsl:template>
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<xsl:template match="BLOCK_DEVICE_INFO">
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