acrn-config: update missing or outdated configuration source code

so that vm_configurations.h/vm_configurations.c are consistent for
same scenario

Upload configuration source code for:
Board               scenarios
whl-ipc-i5          industry, hybrid, hybrid_rt, logical_partiton
whl-ipc-i7          industry, hybrid, hybrid_rt, logical_partiton
ehl-crb-b           industry, hybrid, hybrid_rt, logical_partition
nuc7i7dnb           industry, hybrid, logical_partition

Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>

misc/vm_configs/boards/ehl-crb-b/board.c

@@ -192,8 +192,12 @@ const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
 #define VMSIX_ON_MSI_DEV0	.bdf.bits = {.b = 0x00U, .d = 0x1eU, .f =0x4U},
 #define VMSIX_ON_MSI_DEV1	.bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x1U},
 #define VMSIX_ON_MSI_DEV2	.bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x2U},
+#define VMSIX_ON_MSI_DEV3	.bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x4U},
+#define VMSIX_ON_MSI_DEV4	.bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x5U},
 const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM] = {
 	{VMSIX_ON_MSI_DEV0},
 	{VMSIX_ON_MSI_DEV1},
 	{VMSIX_ON_MSI_DEV2},
+	{VMSIX_ON_MSI_DEV3},
+	{VMSIX_ON_MSI_DEV4},
 };

misc/vm_configs/boards/ehl-crb-b/board_info.h

@@ -8,16 +8,19 @@
 #define BOARD_INFO_H
 
 #define MAX_PCPU_NUM			4U
-#define MAX_VMSIX_ON_MSI_PDEVS_NUM	3U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	5U
 #define MAX_HIDDEN_PDEVS_NUM		0U
 
 #define HI_MMIO_START			~0UL
 #define HI_MMIO_END			0UL
 #define HI_MMIO_SIZE			0x10000000UL
 
+#define P2SB_VGPIO_DM_ENABLED
 #define P2SB_BAR_ADDR			0xFD000000UL
+#define P2SB_BAR_ADDR_GPA		0xFD000000UL
+#define P2SB_BAR_SIZE			0x1000000UL
 
-#define BASE_GPIO_PORT_ID		0x69U
+#define P2SB_BASE_GPIO_PORT_ID		0x69U
-#define MAX_GPIO_COMMUNITIES	0x6U
+#define P2SB_MAX_GPIO_COMMUNITIES	0x6U
 
 #endif /* BOARD_INFO_H */

misc/vm_configs/boards/ehl-crb-b/pci_devices.h

@@ -49,18 +49,22 @@
 
 #define SERIAL_BUS_CONTROLLER_10                .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}
 
+#define COMMUNICATION_CONTROLLER_0              .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x04U}
+
+#define COMMUNICATION_CONTROLLER_1              .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x05U}
+
+#define COMMUNICATION_CONTROLLER_2              .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
+
+#define COMMUNICATION_CONTROLLER_3              .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U}
+
+#define COMMUNICATION_CONTROLLER_4              .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}
+
+#define COMMUNICATION_CONTROLLER_5              .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U}
+
 #define USB_CONTROLLER_0                        .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
 
 #define RAM_MEMORY_0                            .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
 
-#define COMMUNICATION_CONTROLLER_0              .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
-
-#define COMMUNICATION_CONTROLLER_1              .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U}
-
-#define COMMUNICATION_CONTROLLER_2              .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}
-
-#define COMMUNICATION_CONTROLLER_3              .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U}
-
 #define SATA_CONTROLLER_0                       .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
 
 #define SD_HOST_CONTROLLER_0                    .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}

misc/vm_configs/boards/ehl-crb-b/platform_acpi_info.h

@@ -86,4 +86,5 @@
 #define DEFAULT_PCI_MMCFG_START_BUS 	 0x0U
 #define DEFAULT_PCI_MMCFG_END_BUS   	 0xFFU
 
+
 #endif /* PLATFORM_ACPI_INFO_H */

misc/vm_configs/boards/nuc7i7dnb/board.c

@@ -21,6 +21,7 @@
 #include <vtd.h>
 #include <msr.h>
 #include <pci.h>
+#include <misc_cfg.h>
 
 static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
 	{

misc/vm_configs/boards/nuc7i7dnb/platform_acpi_info.h

@@ -69,4 +69,5 @@
 #define DEFAULT_PCI_MMCFG_START_BUS 	 0x0U
 #define DEFAULT_PCI_MMCFG_END_BUS   	 0xFFU
 
+
 #endif /* PLATFORM_ACPI_INFO_H */

misc/vm_configs/boards/whl-ipc-i5/pci_devices.h

@@ -58,6 +58,4 @@
 
 #define ETHERNET_CONTROLLER_1                   .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}
 
-#define IVSHMEM_SHM_REGION_0                    "hv:/shm_region_0"
-
 #endif /* PCI_DEVICES_H_ */

misc/vm_configs/boards/whl-ipc-i5/platform_acpi_info.h

@@ -73,4 +73,5 @@
 #define DEFAULT_PCI_MMCFG_START_BUS 	 0x0U
 #define DEFAULT_PCI_MMCFG_END_BUS   	 0xFFU
 
+
 #endif /* PLATFORM_ACPI_INFO_H */

misc/vm_configs/boards/whl-ipc-i7/platform_acpi_info.h

@@ -73,4 +73,5 @@
 #define DEFAULT_PCI_MMCFG_START_BUS 	 0x0U
 #define DEFAULT_PCI_MMCFG_END_BUS   	 0xFFU
 
+
 #endif /* PLATFORM_ACPI_INFO_H */

misc/vm_configs/scenarios/hybrid/ehl-crb-b/ehl-crb-b.config

@@ -0,0 +1,38 @@
+# Board defconfig generated by acrn-config tool
+
+CONFIG_BOARD="ehl-crb-b"
+CONFIG_HV_RAM_START=0x11000000
+CONFIG_HV_RAM_SIZE=0x9600000
+CONFIG_PLATFORM_RAM_SIZE=0x400000000
+CONFIG_LOW_RAM_SIZE=0x00010000
+CONFIG_SOS_RAM_SIZE=0x400000000
+CONFIG_UOS_RAM_SIZE=0x200000000
+CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
+CONFIG_GPU_SBDF=0x00000010
+CONFIG_UEFI_OS_LOADER_NAME=""
+CONFIG_SCHED_BVT=y
+CONFIG_RELOC=y
+CONFIG_MULTIBOOT2=y
+CONFIG_RDT_ENABLED=n
+CONFIG_CDP_ENABLED=n
+CONFIG_HYPERV_ENABLED=y
+CONFIG_IOMMU_ENFORCE_SNP=n
+CONFIG_ACPI_PARSE_ENABLED=y
+CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
+CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
+CONFIG_IOMMU_BUS_NUM=0x100
+CONFIG_MAX_IOAPIC_NUM=1
+CONFIG_MAX_IR_ENTRIES=256
+CONFIG_MAX_PCI_DEV_NUM=96
+CONFIG_MAX_IOAPIC_LINES=120
+CONFIG_MAX_PT_IRQ_ENTRIES=256
+CONFIG_MAX_MSIX_TABLE_NUM=64
+CONFIG_MAX_EMULATED_MMIO_REGIONS=16
+CONFIG_SERIAL_PCI=y
+CONFIG_SERIAL_PCI_BDF=0xca
+CONFIG_LOG_BUF_SIZE=0x40000
+CONFIG_NPK_LOGLEVEL_DEFAULT=5
+CONFIG_MEM_LOGLEVEL_DEFAULT=5
+CONFIG_LOG_DESTINATION=7
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

misc/vm_configs/scenarios/hybrid/ehl-crb-b/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid/ehl-crb-b/misc_cfg.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MISC_CFG_H
+#define MISC_CFG_H
+
+#define SOS_ROOTFS		"root=/dev/sda3 "
+#define SOS_CONSOLE		"console=ttyS0 "
+#define SOS_COM1_BASE		0x3F8U
+#define SOS_COM1_IRQ		4U
+#define SOS_COM2_BASE		0x2F8U
+#define SOS_COM2_IRQ		5U
+
+#define SOS_BOOTARGS_DIFF	"rw " \
+				"rootwait "	\
+				"console=tty0 "	\
+				"consoleblank=0 "	\
+				"no_timer_check "	\
+				"quiet "	\
+				"loglevel=3 "	\
+				"i915.nuclear_pageflip=1 "	\
+				"swiotlb=131072 "	\
+				"maxcpus=3"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U))
+
+#ifdef CONFIG_RDT_ENABLED
+#define HV_SUPPORTED_MAX_CLOS	0U
+#define MAX_MBA_CLOS_NUM_ENTRIES	0U
+#define MAX_CACHE_CLOS_NUM_ENTRIES	0U
+
+#define CLOS_MASK_0			0xfffU
+#define CLOS_MASK_1			0xfffU
+#define CLOS_MASK_2			0xfffU
+#define CLOS_MASK_3			0xfffU
+#define CLOS_MASK_4			0xfffU
+#define CLOS_MASK_5			0xfffU
+#define CLOS_MASK_6			0xfffU
+#define CLOS_MASK_7			0xfffU
+#define CLOS_MASK_8			0xfffU
+#define CLOS_MASK_9			0xfffU
+#define CLOS_MASK_10			0xfffU
+#define CLOS_MASK_11			0xfffU
+#define CLOS_MASK_12			0xfffU
+#define CLOS_MASK_13			0xfffU
+#define CLOS_MASK_14			0xfffU
+#define CLOS_MASK_15			0xfffU
+
+#define VM0_VCPU_CLOS			{0U}
+#define VM1_VCPU_CLOS			{0U}
+#define VM2_VCPU_CLOS			{0U}
+#endif
+
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	1U
+
+
+#define VM0_PT_INTX_NUM	0U
+
+#endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid/ehl-crb-b/pci_dev.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+#include <pci_devices.h>
+#include <vpci.h>
+#include <vbar_base.h>
+#include <mmu.h>
+#include <page.h>

misc/vm_configs/scenarios/hybrid/ehl-crb-b/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid/ehl-crb-b/vbar_base.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef VBAR_BASE_H_
+#define VBAR_BASE_H_
+
+#define VGA_COMPATIBLE_CONTROLLER_0_VBAR              .vbar_base[0] = 0x82000000UL, \
+                                                      .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL
+
+#define SYSTEM_PERIPHERAL_0_VBAR                      .vbar_base[0] = 0x834e4000UL
+
+#define SYSTEM_PERIPHERAL_1_VBAR                      .vbar_base[0] = 0x83000000UL
+
+#define SERIAL_BUS_CONTROLLER_0_VBAR                  .vbar_base[0] = 0x83441000UL
+
+#define SERIAL_BUS_CONTROLLER_1_VBAR                  .vbar_base[0] = 0x83444000UL
+
+#define SERIAL_BUS_CONTROLLER_2_VBAR                  .vbar_base[0] = 0x834d8000UL
+
+#define SERIAL_BUS_CONTROLLER_3_VBAR                  .vbar_base[0] = 0x83445000UL
+
+#define SERIAL_BUS_CONTROLLER_4_VBAR                  .vbar_base[0] = 0x83446000UL
+
+#define SERIAL_BUS_CONTROLLER_5_VBAR                  .vbar_base[0] = 0x83447000UL
+
+#define SERIAL_BUS_CONTROLLER_6_VBAR                  .vbar_base[0] = 0x83448000UL
+
+#define SERIAL_BUS_CONTROLLER_7_VBAR                  .vbar_base[0] = 0x834da000UL
+
+#define SERIAL_BUS_CONTROLLER_8_VBAR                  .vbar_base[0] = 0x834dc000UL
+
+#define SERIAL_BUS_CONTROLLER_9_VBAR                  .vbar_base[0] = 0x834de000UL
+
+#define SERIAL_BUS_CONTROLLER_10_VBAR                 .vbar_base[0] = 0x8344c000UL, \
+                                                      .vbar_base[1] = 0x80000000UL
+
+#define COMMUNICATION_CONTROLLER_0_VBAR               .vbar_base[0] = 0x84600000UL
+
+#define COMMUNICATION_CONTROLLER_1_VBAR               .vbar_base[0] = 0x845fc000UL
+
+#define COMMUNICATION_CONTROLLER_2_VBAR               .vbar_base[0] = 0x834eb000UL
+
+#define COMMUNICATION_CONTROLLER_3_VBAR               .vbar_base[0] = 0x83449000UL
+
+#define COMMUNICATION_CONTROLLER_4_VBAR               .vbar_base[0] = 0x8344a000UL
+
+#define COMMUNICATION_CONTROLLER_5_VBAR               .vbar_base[0] = 0x8344b000UL
+
+#define USB_CONTROLLER_0_VBAR                         .vbar_base[0] = 0x834c0000UL
+
+#define RAM_MEMORY_0_VBAR                             .vbar_base[0] = 0x834d0000UL, \
+                                                      .vbar_base[2] = 0x834e7000UL
+
+#define SATA_CONTROLLER_0_VBAR                        .vbar_base[0] = 0x834e2000UL, \
+                                                      .vbar_base[1] = 0x834f6000UL, \
+                                                      .vbar_base[5] = 0x834f5000UL
+
+#define SD_HOST_CONTROLLER_0_VBAR                     .vbar_base[0] = 0x834ee000UL
+
+#define SD_HOST_CONTROLLER_1_VBAR                     .vbar_base[0] = 0x834ef000UL
+
+#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR            .vbar_base[0] = 0x83400000UL
+
+#define ETHERNET_CONTROLLER_0_VBAR                    .vbar_base[0] = 0x83500000UL
+
+#define ETHERNET_CONTROLLER_1_VBAR                    .vbar_base[0] = 0x83480000UL
+
+#define ETHERNET_CONTROLLER_2_VBAR                    .vbar_base[0] = 0x83442000UL, \
+                                                      .vbar_base[2] = 0x834f2000UL
+
+#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR            .vbar_base[0] = 0x834d4000UL, \
+                                                      .vbar_base[4] = 0x83200000UL
+
+#define SMBUS_0_VBAR                                  .vbar_base[0] = 0x834f3000UL
+
+#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR         .vbar_base[0] = 0x83300000UL
+
+#endif /* VBAR_BASE_H_ */

misc/vm_configs/scenarios/hybrid/nuc7i7dnb/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h

@@ -23,28 +23,23 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=3"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_CONFIG_PCI_DEV_NUM	1U
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid/nuc7i7dnb/nuc7i7dnb.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/hybrid/nuc7i7dnb/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid/vm_configurations.c

@@ -7,12 +7,17 @@
 #include <vuart.h>
 #include <pci_dev.h>
 
+extern struct pt_intx_config vm0_pt_intx[1U];
+
 struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	{	/* VM0 */
 		CONFIG_SAFETY_VM(1),
 		.name = "ACRN PRE-LAUNCHED VM0",
 		.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
 		.guest_flags = 0UL,
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM0_VCPU_CLOS,
+#endif
 		.memory = {
 			.start_hpa = VM0_CONFIG_MEM_START_HPA,
 			.size = VM0_CONFIG_MEM_SIZE,
@@ -26,6 +31,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 			.kernel_load_addr = 0x8000,
 			.kernel_entry_addr = 0x8000,
 		},
+		.acpi_config = {
+			.acpi_mod_tag = "ACPI_VM0",
+		},
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,
 			.addr.port_base = COM1_BASE,
@@ -38,14 +46,24 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 			.t_vuart.vm_id = 1U,
 			.t_vuart.vuart_id = 1U,
 		},
+#ifdef VM0_PASSTHROUGH_TPM
+		.pt_tpm2 = true,
+		.mmiodevs[0] = {
+			.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
+			.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
+			.size = VM0_TPM_BUFFER_SIZE,
+		},
+#endif
 #ifdef P2SB_BAR_ADDR
 		.pt_p2sb_bar = true,
 		.mmiodevs[0] = {
-			.base_gpa = 0xFD000000UL,
+			.base_gpa = P2SB_BAR_ADDR_GPA,
 			.base_hpa = P2SB_BAR_ADDR,
-			.size = 0x1000000UL,
+			.size = P2SB_BAR_SIZE,
 		},
 #endif
+		.pt_intx_num = VM0_PT_INTX_NUM,
+		.pt_intx = &vm0_pt_intx[0U],
 	},
 	{	/* VM1 */
 		CONFIG_SOS_VM,
@@ -53,6 +71,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 
 		/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
 		.guest_flags = 0UL,
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM1_VCPU_CLOS,
+#endif
 		.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
 		.memory = {
 			.start_hpa = 0UL,
@@ -79,6 +100,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	},
 	{	/* VM2 */
 		CONFIG_POST_STD_VM(1),
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM2_VCPU_CLOS,
+#endif
 		.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,

misc/vm_configs/scenarios/hybrid/vm_configurations.h

@@ -22,12 +22,10 @@
 #define DM_OWNED_GUEST_FLAG_MASK        (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
 						GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
 
-#define VM0_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(3U))
 #define VM0_CONFIG_MEM_START_HPA        0x100000000UL
 #define VM0_CONFIG_MEM_SIZE             0x20000000UL
 #define VM0_CONFIG_MEM_START_HPA2       0x0UL
 #define VM0_CONFIG_MEM_SIZE_HPA2        0x0UL
-#define VM0_CONFIG_PCI_DEV_NUM          1U
 
 /* SOS_VM == VM1 */
 #define SOS_VM_BOOTARGS			SOS_ROOTFS	\
@@ -35,8 +33,4 @@
 					SOS_IDLE	\
 					SOS_BOOTARGS_DIFF
 
-#define SOS_VM_CONFIG_CPU_AFFINITY      (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
-
-#define VM2_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(2U))
-
 #endif /* VM_CONFIGURATIONS_H */

misc/vm_configs/scenarios/hybrid/whl-ipc-i5/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h

@@ -23,28 +23,28 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=3"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	1U
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid/whl-ipc-i5/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid/whl-ipc-i5/whl-ipc-i5.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/hybrid/whl-ipc-i7/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h

@@ -23,28 +23,28 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=3"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	1U
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid/whl-ipc-i7/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid/whl-ipc-i7/whl-ipc-i7.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/ehl-crb-b.config

@@ -0,0 +1,38 @@
+# Board defconfig generated by acrn-config tool
+
+CONFIG_BOARD="ehl-crb-b"
+CONFIG_HV_RAM_START=0x11000000
+CONFIG_HV_RAM_SIZE=0x9800000
+CONFIG_PLATFORM_RAM_SIZE=0x400000000
+CONFIG_LOW_RAM_SIZE=0x00010000
+CONFIG_SOS_RAM_SIZE=0x400000000
+CONFIG_UOS_RAM_SIZE=0x200000000
+CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=y
+CONFIG_GPU_SBDF=0x00000010
+CONFIG_UEFI_OS_LOADER_NAME=""
+CONFIG_SCHED_BVT=y
+CONFIG_RELOC=y
+CONFIG_MULTIBOOT2=y
+CONFIG_RDT_ENABLED=n
+CONFIG_CDP_ENABLED=n
+CONFIG_HYPERV_ENABLED=y
+CONFIG_IOMMU_ENFORCE_SNP=n
+CONFIG_ACPI_PARSE_ENABLED=y
+CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
+CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
+CONFIG_IOMMU_BUS_NUM=0x100
+CONFIG_MAX_IOAPIC_NUM=1
+CONFIG_MAX_IR_ENTRIES=256
+CONFIG_MAX_PCI_DEV_NUM=96
+CONFIG_MAX_IOAPIC_LINES=120
+CONFIG_MAX_PT_IRQ_ENTRIES=256
+CONFIG_MAX_MSIX_TABLE_NUM=64
+CONFIG_MAX_EMULATED_MMIO_REGIONS=16
+CONFIG_SERIAL_PCI=y
+CONFIG_SERIAL_PCI_BDF=0xca
+CONFIG_LOG_BUF_SIZE=0x40000
+CONFIG_NPK_LOGLEVEL_DEFAULT=5
+CONFIG_MEM_LOGLEVEL_DEFAULT=5
+CONFIG_LOG_DESTINATION=7
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/ivshmem_cfg.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#include <ivshmem.h>
+#include <pgtable.h>
+#include <pci_devices.h>
+
+/*
+ * The IVSHMEM_SHM_SIZE is the sum of all memory regions.
+ * The size range of each memory region is [2MB, 512MB] and is a power of 2.
+ */
+#define IVSHMEM_SHM_SIZE	0x200000UL
+#define IVSHMEM_DEV_NUM		2UL
+
+/* All user defined memory regions */
+
+struct ivshmem_shm_region mem_regions[] = {
+	{
+		.name = IVSHMEM_SHM_REGION_0,
+		.size = 0x200000UL,		/* 2M */
+	},
+};
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MISC_CFG_H
+#define MISC_CFG_H
+
+#define SOS_ROOTFS		"root=/dev/mmcblk0p2 "
+#define SOS_CONSOLE		"console=ttyS0 "
+#define SOS_COM1_BASE		0x3F8U
+#define SOS_COM1_IRQ		4U
+#define SOS_COM2_BASE		0x2F8U
+#define SOS_COM2_IRQ		5U
+
+#define SOS_BOOTARGS_DIFF	"rw " \
+				"rootwait "	\
+				"console=tty0 "	\
+				"consoleblank=0 "	\
+				"no_timer_check "	\
+				"quiet "	\
+				"loglevel=3 "	\
+				"i915.nuclear_pageflip=1 "	\
+				"swiotlb=131072 "	\
+				"maxcpus=2"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U))
+
+#ifdef CONFIG_RDT_ENABLED
+#define HV_SUPPORTED_MAX_CLOS	0U
+#define MAX_MBA_CLOS_NUM_ENTRIES	0U
+#define MAX_CACHE_CLOS_NUM_ENTRIES	0U
+
+#define CLOS_MASK_0			0xfffU
+#define CLOS_MASK_1			0xfffU
+#define CLOS_MASK_2			0xfffU
+#define CLOS_MASK_3			0xfffU
+#define CLOS_MASK_4			0xfffU
+#define CLOS_MASK_5			0xfffU
+#define CLOS_MASK_6			0xfffU
+#define CLOS_MASK_7			0xfffU
+#define CLOS_MASK_8			0xfffU
+#define CLOS_MASK_9			0xfffU
+#define CLOS_MASK_10			0xfffU
+#define CLOS_MASK_11			0xfffU
+#define CLOS_MASK_12			0xfffU
+#define CLOS_MASK_13			0xfffU
+#define CLOS_MASK_14			0xfffU
+#define CLOS_MASK_15			0xfffU
+
+#define VM0_VCPU_CLOS			{0U}
+#define VM1_VCPU_CLOS			{0U}
+#define VM2_VCPU_CLOS			{0U}
+#endif
+
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	4U
+#define VM2_CONFIG_PCI_DEV_NUM	1U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda2 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
+#endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/pci_dev.c

@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+#include <pci_devices.h>
+#include <vpci.h>
+#include <vbar_base.h>
+#include <mmu.h>
+#include <page.h>
+#include <ivshmem.h>
+
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
+#define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
+
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
+struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
+		.vdev_ops = &vhostbridge_ops,
+	},
+	{
+		.emu_type = PCI_DEV_TYPE_PTDEV,
+		.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
+		PTDEV(SATA_CONTROLLER_0),
+	},
+	{
+		.emu_type = PCI_DEV_TYPE_PTDEV,
+		.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
+		PTDEV(ETHERNET_CONTROLLER_1),
+	},
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U},
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0,
+		IVSHMEM_DEVICE_0_VBAR
+	},
+};
+
+struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = {
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.value = UNASSIGNED_VBDF,
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0
+	},
+};

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/vbar_base.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef VBAR_BASE_H_
+#define VBAR_BASE_H_
+
+#define VGA_COMPATIBLE_CONTROLLER_0_VBAR              .vbar_base[0] = 0x82000000UL, \
+                                                      .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL
+
+#define SYSTEM_PERIPHERAL_0_VBAR                      .vbar_base[0] = 0x834e4000UL
+
+#define SYSTEM_PERIPHERAL_1_VBAR                      .vbar_base[0] = 0x83000000UL
+
+#define SERIAL_BUS_CONTROLLER_0_VBAR                  .vbar_base[0] = 0x83441000UL
+
+#define SERIAL_BUS_CONTROLLER_1_VBAR                  .vbar_base[0] = 0x83444000UL
+
+#define SERIAL_BUS_CONTROLLER_2_VBAR                  .vbar_base[0] = 0x834d8000UL
+
+#define SERIAL_BUS_CONTROLLER_3_VBAR                  .vbar_base[0] = 0x83445000UL
+
+#define SERIAL_BUS_CONTROLLER_4_VBAR                  .vbar_base[0] = 0x83446000UL
+
+#define SERIAL_BUS_CONTROLLER_5_VBAR                  .vbar_base[0] = 0x83447000UL
+
+#define SERIAL_BUS_CONTROLLER_6_VBAR                  .vbar_base[0] = 0x83448000UL
+
+#define SERIAL_BUS_CONTROLLER_7_VBAR                  .vbar_base[0] = 0x834da000UL
+
+#define SERIAL_BUS_CONTROLLER_8_VBAR                  .vbar_base[0] = 0x834dc000UL
+
+#define SERIAL_BUS_CONTROLLER_9_VBAR                  .vbar_base[0] = 0x834de000UL
+
+#define SERIAL_BUS_CONTROLLER_10_VBAR                 .vbar_base[0] = 0x8344c000UL, \
+                                                      .vbar_base[1] = 0x80000000UL
+
+#define COMMUNICATION_CONTROLLER_0_VBAR               .vbar_base[0] = 0x84600000UL
+
+#define COMMUNICATION_CONTROLLER_1_VBAR               .vbar_base[0] = 0x845fc000UL
+
+#define COMMUNICATION_CONTROLLER_2_VBAR               .vbar_base[0] = 0x834eb000UL
+
+#define COMMUNICATION_CONTROLLER_3_VBAR               .vbar_base[0] = 0x83449000UL
+
+#define COMMUNICATION_CONTROLLER_4_VBAR               .vbar_base[0] = 0x8344a000UL
+
+#define COMMUNICATION_CONTROLLER_5_VBAR               .vbar_base[0] = 0x8344b000UL
+
+#define USB_CONTROLLER_0_VBAR                         .vbar_base[0] = 0x834c0000UL
+
+#define RAM_MEMORY_0_VBAR                             .vbar_base[0] = 0x834d0000UL, \
+                                                      .vbar_base[2] = 0x834e7000UL
+
+#define SATA_CONTROLLER_0_VBAR                        .vbar_base[0] = 0x834e2000UL, \
+                                                      .vbar_base[1] = 0x834f6000UL, \
+                                                      .vbar_base[5] = 0x834f5000UL
+
+#define SD_HOST_CONTROLLER_0_VBAR                     .vbar_base[0] = 0x834ee000UL
+
+#define SD_HOST_CONTROLLER_1_VBAR                     .vbar_base[0] = 0x834ef000UL
+
+#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR            .vbar_base[0] = 0x83400000UL
+
+#define ETHERNET_CONTROLLER_0_VBAR                    .vbar_base[0] = 0x83500000UL
+
+#define ETHERNET_CONTROLLER_1_VBAR                    .vbar_base[0] = 0x83480000UL
+
+#define ETHERNET_CONTROLLER_2_VBAR                    .vbar_base[0] = 0x83442000UL, \
+                                                      .vbar_base[2] = 0x834f2000UL
+
+#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR            .vbar_base[0] = 0x834d4000UL, \
+                                                      .vbar_base[4] = 0x83200000UL
+
+#define SMBUS_0_VBAR                                  .vbar_base[0] = 0x834f3000UL
+
+#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR         .vbar_base[0] = 0x83300000UL
+
+#define IVSHMEM_DEVICE_0_VBAR                         .vbar_base[0] = 0x100000000UL, \
+                                                      .vbar_base[2] = 0x10020000cUL
+
+#endif /* VBAR_BASE_H_ */

misc/vm_configs/scenarios/hybrid_rt/vm_configurations.c

@@ -10,12 +10,17 @@
 extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
 extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM];
 
+extern struct pt_intx_config vm0_pt_intx[1U];
+
 struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	{	/* VM0 */
 		CONFIG_PRE_RT_VM(1),
 		.name = "ACRN PRE-LAUNCHED VM0",
 		.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
 		.guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT),
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM0_VCPU_CLOS,
+#endif
 		.memory = {
 			.start_hpa = VM0_CONFIG_MEM_START_HPA,
 			.size = VM0_CONFIG_MEM_SIZE,
@@ -26,9 +31,10 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 			.name = "PREEMPT-RT",
 			.kernel_type = KERNEL_BZIMAGE,
 			.kernel_mod_tag = "RT_bzImage",
-			.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
+			.bootargs = VM0_BOOT_ARGS,
-				noxsave nohpet no_timer_check ignore_loglevel \
+		},
-				consoleblank=0 tsc=reliable "
+		.acpi_config = {
+			.acpi_mod_tag = "ACPI_VM0",
 		},
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,
@@ -47,11 +53,21 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 #ifdef VM0_PASSTHROUGH_TPM
 		.pt_tpm2 = true,
 		.mmiodevs[0] = {
-			.base_gpa = 0xFED40000UL,
+			.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
 			.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
 			.size = VM0_TPM_BUFFER_SIZE,
 		},
 #endif
+#ifdef P2SB_BAR_ADDR
+		.pt_p2sb_bar = true,
+		.mmiodevs[0] = {
+			.base_gpa = P2SB_BAR_ADDR_GPA,
+			.base_hpa = P2SB_BAR_ADDR,
+			.size = P2SB_BAR_SIZE,
+		},
+#endif
+		.pt_intx_num = VM0_PT_INTX_NUM,
+		.pt_intx = &vm0_pt_intx[0U],
 	},
 	{	/* VM1 */
 		CONFIG_SOS_VM,
@@ -59,6 +75,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 
 		/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
 		.guest_flags = 0UL,
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM1_VCPU_CLOS,
+#endif
 		.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
 		.memory = {
 			.start_hpa = 0UL,
@@ -85,6 +104,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	},
 	{	/* VM2 */
 		CONFIG_POST_STD_VM(1),
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM2_VCPU_CLOS,
+#endif
 		/* The PCI device configuration is only for in-hypervisor vPCI devices. */
 		.pci_dev_num = VM2_CONFIG_PCI_DEV_NUM,
 		.pci_devs = vm2_pci_devs,

misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h

@@ -22,12 +22,10 @@
 #define DM_OWNED_GUEST_FLAG_MASK        (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
 						GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
 
-#define VM0_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
 #define VM0_CONFIG_MEM_START_HPA        0x100000000UL
 #define VM0_CONFIG_MEM_SIZE             0x40000000UL
 #define VM0_CONFIG_MEM_START_HPA2       0x0UL
 #define VM0_CONFIG_MEM_SIZE_HPA2        0x0UL
-#define VM0_CONFIG_PCI_DEV_NUM          4U
 
 /* SOS_VM == VM1 */
 #define SOS_VM_BOOTARGS			SOS_ROOTFS	\
@@ -35,9 +33,4 @@
 					SOS_IDLE	\
 					SOS_BOOTARGS_DIFF
 
-#define SOS_VM_CONFIG_CPU_AFFINITY      (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-
-#define VM2_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(1U))
-#define VM2_CONFIG_PCI_DEV_NUM          1U
-
 #endif /* VM_CONFIGURATIONS_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h

@@ -23,32 +23,33 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=2"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
 #define VM0_PASSTHROUGH_TPM
 #define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
 #define VM0_TPM_BUFFER_SIZE        0x5000UL
 
+#define VM0_CONFIG_PCI_DEV_NUM	4U
+#define VM2_CONFIG_PCI_DEV_NUM	1U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/whl-ipc-i5.config

@@ -2,7 +2,7 @@
 
 CONFIG_BOARD="whl-ipc-i5"
 CONFIG_HV_RAM_START=0x11000000
-CONFIG_HV_RAM_SIZE=0x9600000
+CONFIG_HV_RAM_SIZE=0x9800000
 CONFIG_PLATFORM_RAM_SIZE=0x400000000
 CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/ivshmem_cfg.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#include <ivshmem.h>
+#include <pgtable.h>
+#include <pci_devices.h>
+
+/*
+ * The IVSHMEM_SHM_SIZE is the sum of all memory regions.
+ * The size range of each memory region is [2MB, 512MB] and is a power of 2.
+ */
+#define IVSHMEM_SHM_SIZE	0x200000UL
+#define IVSHMEM_DEV_NUM		2UL
+
+/* All user defined memory regions */
+
+struct ivshmem_shm_region mem_regions[] = {
+	{
+		.name = IVSHMEM_SHM_REGION_0,
+		.size = 0x200000UL,		/* 2M */
+	},
+};
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h

@@ -23,32 +23,33 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=2"
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
 #define VM0_PASSTHROUGH_TPM
 #define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
 #define VM0_TPM_BUFFER_SIZE        0x5000UL
 
+#define VM0_CONFIG_PCI_DEV_NUM	4U
+#define VM2_CONFIG_PCI_DEV_NUM	1U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/pci_dev.c

@@ -10,9 +10,18 @@
 #include <vbar_base.h>
 #include <mmu.h>
 #include <page.h>
+#include <ivshmem.h>
 
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
 #define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,
@@ -29,4 +38,20 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 		.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
 		PTDEV(ETHERNET_CONTROLLER_0),
 	},
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U},
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0,
+		IVSHMEM_DEVICE_0_VBAR
+	},
+};
+
+struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = {
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.value = UNASSIGNED_VBDF,
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0
+	},
 };

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/vbar_base.h

@@ -40,4 +40,7 @@
 #define ETHERNET_CONTROLLER_1_VBAR                    .vbar_base[0] = 0xa1100000UL, \
                                                       .vbar_base[3] = 0xa1120000UL
 
+#define IVSHMEM_DEVICE_0_VBAR                         .vbar_base[0] = 0x80000000UL, \
+                                                      .vbar_base[2] = 0x10000000cUL
+
 #endif /* VBAR_BASE_H_ */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/whl-ipc-i7.config

@@ -2,12 +2,13 @@
 
 CONFIG_BOARD="whl-ipc-i7"
 CONFIG_HV_RAM_START=0x11000000
-CONFIG_HV_RAM_SIZE=0x9600000
+CONFIG_HV_RAM_SIZE=0x9800000
 CONFIG_PLATFORM_RAM_SIZE=0x400000000
 CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=y
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/industry/ehl-crb-b/ehl-crb-b.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
 CONFIG_SCHED_BVT=y
@@ -28,8 +29,8 @@ CONFIG_MAX_IOAPIC_LINES=120
 CONFIG_MAX_PT_IRQ_ENTRIES=256
 CONFIG_MAX_MSIX_TABLE_NUM=64
 CONFIG_MAX_EMULATED_MMIO_REGIONS=16
-CONFIG_SERIAL_PCI=y
+CONFIG_SERIAL_MMIO=y
-CONFIG_SERIAL_PCI_BDF="00:19.2"
+CONFIG_SERIAL_MMIO_BASE=0xfe042000
 CONFIG_LOG_BUF_SIZE=0x40000
 CONFIG_NPK_LOGLEVEL_DEFAULT=5
 CONFIG_MEM_LOGLEVEL_DEFAULT=5

misc/vm_configs/scenarios/industry/ehl-crb-b/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h

@@ -8,10 +8,10 @@
 #define MISC_CFG_H
 
 #define SOS_ROOTFS		"root=/dev/mmcblk0p2 "
-#define SOS_CONSOLE		"console=ttyS0 "
+#define SOS_CONSOLE		"console=ttyS3 "
-#define SOS_COM1_BASE		0x3F8U
+#define SOS_COM1_BASE		0x2E8U
 #define SOS_COM1_IRQ		3U
-#define SOS_COM2_BASE		0x2E8U
+#define SOS_COM2_BASE		0x3F8U
 #define SOS_COM2_IRQ		4U
 
 #define SOS_BOOTARGS_DIFF	"rw " \
@@ -21,7 +21,19 @@
 				"no_timer_check "	\
 				"quiet "	\
 				"loglevel=3 "	\
-				"i915.nuclear_pageflip=1"
+				"i915.nuclear_pageflip=1 "	\
+				"swiotlb=131072 "	\
+				"maxcpus=4"
+
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM3_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM4_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM5_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM6_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM7_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
 #define HV_SUPPORTED_MAX_CLOS	16U
@@ -55,4 +67,8 @@
 #define VM7_VCPU_CLOS			{0U, 0U}
 #endif
 
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/industry/ehl-crb-b/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/industry/nuc7i7dnb/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h

@@ -23,28 +23,27 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=4"
+
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM3_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM4_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM5_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM6_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM7_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/industry/nuc7i7dnb/nuc7i7dnb.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/industry/nuc7i7dnb/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/industry/vm_configurations.c

@@ -7,6 +7,8 @@
 #include <vuart.h>
 #include <pci_dev.h>
 
+extern struct pt_intx_config vm0_pt_intx[1U];
+
 struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	{	/* VM0 */
 		CONFIG_SOS_VM,

misc/vm_configs/scenarios/industry/vm_configurations.h

@@ -28,14 +28,4 @@
 					SOS_IDLE	\
 					SOS_BOOTARGS_DIFF
 
-#define SOS_VM_CONFIG_CPU_AFFINITY      (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
-
-#define VM1_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-#define VM2_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
-#define VM3_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-#define VM4_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-#define VM5_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-#define VM6_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-#define VM7_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
-
 #endif /* VM_CONFIGURATIONS_H */

misc/vm_configs/scenarios/industry/whl-ipc-i5/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h

@@ -23,28 +23,27 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=4"
+
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM3_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM4_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM5_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM6_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM7_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/industry/whl-ipc-i5/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/industry/whl-ipc-i5/whl-ipc-i5.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/industry/whl-ipc-i7/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h

@@ -23,28 +23,27 @@
 				"loglevel=3 "	\
 				"i915.nuclear_pageflip=1 "	\
 				"hvlog=2M@0xe00000 "	\
-				"memmap=0x200000$0xe00000"
+				"memmap=0x200000$0xe00000 "	\
+				"maxcpus=4"
+
+
+#define SOS_VM_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM2_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
+#define VM3_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM4_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM5_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM6_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
+#define VM7_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
 
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/industry/whl-ipc-i7/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/industry/whl-ipc-i7/whl-ipc-i7.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/ehl-crb-b.config

@@ -0,0 +1,38 @@
+# Board defconfig generated by acrn-config tool
+
+CONFIG_BOARD="ehl-crb-b"
+CONFIG_HV_RAM_START=0x11000000
+CONFIG_HV_RAM_SIZE=0x7800000
+CONFIG_PLATFORM_RAM_SIZE=0x400000000
+CONFIG_LOW_RAM_SIZE=0x00010000
+CONFIG_SOS_RAM_SIZE=0x400000000
+CONFIG_UOS_RAM_SIZE=0x200000000
+CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
+CONFIG_GPU_SBDF=0x00000010
+CONFIG_UEFI_OS_LOADER_NAME=""
+CONFIG_SCHED_BVT=y
+CONFIG_RELOC=y
+CONFIG_MULTIBOOT2=y
+CONFIG_RDT_ENABLED=n
+CONFIG_CDP_ENABLED=n
+CONFIG_HYPERV_ENABLED=y
+CONFIG_IOMMU_ENFORCE_SNP=n
+CONFIG_ACPI_PARSE_ENABLED=y
+CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
+CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
+CONFIG_IOMMU_BUS_NUM=0x100
+CONFIG_MAX_IOAPIC_NUM=1
+CONFIG_MAX_IR_ENTRIES=256
+CONFIG_MAX_PCI_DEV_NUM=96
+CONFIG_MAX_IOAPIC_LINES=120
+CONFIG_MAX_PT_IRQ_ENTRIES=64
+CONFIG_MAX_MSIX_TABLE_NUM=64
+CONFIG_MAX_EMULATED_MMIO_REGIONS=16
+CONFIG_SERIAL_PCI=y
+CONFIG_SERIAL_PCI_BDF=0xca
+CONFIG_LOG_BUF_SIZE=0x40000
+CONFIG_NPK_LOGLEVEL_DEFAULT=5
+CONFIG_MEM_LOGLEVEL_DEFAULT=5
+CONFIG_LOG_DESTINATION=7
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/misc_cfg.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MISC_CFG_H
+#define MISC_CFG_H
+
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
+
+#ifdef CONFIG_RDT_ENABLED
+#define HV_SUPPORTED_MAX_CLOS	0U
+#define MAX_MBA_CLOS_NUM_ENTRIES	0U
+#define MAX_CACHE_CLOS_NUM_ENTRIES	0U
+
+#define CLOS_MASK_0			0xfffU
+#define CLOS_MASK_1			0xfffU
+#define CLOS_MASK_2			0xfffU
+#define CLOS_MASK_3			0xfffU
+#define CLOS_MASK_4			0xfffU
+#define CLOS_MASK_5			0xfffU
+#define CLOS_MASK_6			0xfffU
+#define CLOS_MASK_7			0xfffU
+#define CLOS_MASK_8			0xfffU
+#define CLOS_MASK_9			0xfffU
+#define CLOS_MASK_10			0xfffU
+#define CLOS_MASK_11			0xfffU
+#define CLOS_MASK_12			0xfffU
+#define CLOS_MASK_13			0xfffU
+#define CLOS_MASK_14			0xfffU
+#define CLOS_MASK_15			0xfffU
+
+#define VM0_VCPU_CLOS			{0U, 0U}
+#define VM1_VCPU_CLOS			{0U, 0U}
+#endif
+
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	1U
+#define VM1_CONFIG_PCI_DEV_NUM	1U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+#define VM1_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
+#endif /* MISC_CFG_H */

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/pci_dev.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+#include <pci_devices.h>
+#include <vpci.h>
+#include <vbar_base.h>
+#include <mmu.h>
+#include <page.h>

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/logical_partition/ehl-crb-b/vbar_base.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef VBAR_BASE_H_
+#define VBAR_BASE_H_
+
+#define VGA_COMPATIBLE_CONTROLLER_0_VBAR              .vbar_base[0] = 0x82000000UL, \
+                                                      .vbar_base[2] = PTDEV_HI_MMIO_START + 0x0UL
+
+#define SYSTEM_PERIPHERAL_0_VBAR                      .vbar_base[0] = 0x834e4000UL
+
+#define SYSTEM_PERIPHERAL_1_VBAR                      .vbar_base[0] = 0x83000000UL
+
+#define SERIAL_BUS_CONTROLLER_0_VBAR                  .vbar_base[0] = 0x83441000UL
+
+#define SERIAL_BUS_CONTROLLER_1_VBAR                  .vbar_base[0] = 0x83444000UL
+
+#define SERIAL_BUS_CONTROLLER_2_VBAR                  .vbar_base[0] = 0x834d8000UL
+
+#define SERIAL_BUS_CONTROLLER_3_VBAR                  .vbar_base[0] = 0x83445000UL
+
+#define SERIAL_BUS_CONTROLLER_4_VBAR                  .vbar_base[0] = 0x83446000UL
+
+#define SERIAL_BUS_CONTROLLER_5_VBAR                  .vbar_base[0] = 0x83447000UL
+
+#define SERIAL_BUS_CONTROLLER_6_VBAR                  .vbar_base[0] = 0x83448000UL
+
+#define SERIAL_BUS_CONTROLLER_7_VBAR                  .vbar_base[0] = 0x834da000UL
+
+#define SERIAL_BUS_CONTROLLER_8_VBAR                  .vbar_base[0] = 0x834dc000UL
+
+#define SERIAL_BUS_CONTROLLER_9_VBAR                  .vbar_base[0] = 0x834de000UL
+
+#define SERIAL_BUS_CONTROLLER_10_VBAR                 .vbar_base[0] = 0x8344c000UL, \
+                                                      .vbar_base[1] = 0x80000000UL
+
+#define COMMUNICATION_CONTROLLER_0_VBAR               .vbar_base[0] = 0x84600000UL
+
+#define COMMUNICATION_CONTROLLER_1_VBAR               .vbar_base[0] = 0x845fc000UL
+
+#define COMMUNICATION_CONTROLLER_2_VBAR               .vbar_base[0] = 0x834eb000UL
+
+#define COMMUNICATION_CONTROLLER_3_VBAR               .vbar_base[0] = 0x83449000UL
+
+#define COMMUNICATION_CONTROLLER_4_VBAR               .vbar_base[0] = 0x8344a000UL
+
+#define COMMUNICATION_CONTROLLER_5_VBAR               .vbar_base[0] = 0x8344b000UL
+
+#define USB_CONTROLLER_0_VBAR                         .vbar_base[0] = 0x834c0000UL
+
+#define RAM_MEMORY_0_VBAR                             .vbar_base[0] = 0x834d0000UL, \
+                                                      .vbar_base[2] = 0x834e7000UL
+
+#define SATA_CONTROLLER_0_VBAR                        .vbar_base[0] = 0x834e2000UL, \
+                                                      .vbar_base[1] = 0x834f6000UL, \
+                                                      .vbar_base[5] = 0x834f5000UL
+
+#define SD_HOST_CONTROLLER_0_VBAR                     .vbar_base[0] = 0x834ee000UL
+
+#define SD_HOST_CONTROLLER_1_VBAR                     .vbar_base[0] = 0x834ef000UL
+
+#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR            .vbar_base[0] = 0x83400000UL
+
+#define ETHERNET_CONTROLLER_0_VBAR                    .vbar_base[0] = 0x83500000UL
+
+#define ETHERNET_CONTROLLER_1_VBAR                    .vbar_base[0] = 0x83480000UL
+
+#define ETHERNET_CONTROLLER_2_VBAR                    .vbar_base[0] = 0x83442000UL, \
+                                                      .vbar_base[2] = 0x834f2000UL
+
+#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR            .vbar_base[0] = 0x834d4000UL, \
+                                                      .vbar_base[4] = 0x83200000UL
+
+#define SMBUS_0_VBAR                                  .vbar_base[0] = 0x834f3000UL
+
+#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR         .vbar_base[0] = 0x83300000UL
+
+#endif /* VBAR_BASE_H_ */

misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h

@@ -7,26 +7,27 @@
 #ifndef MISC_CFG_H
 #define MISC_CFG_H
 
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
+
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_CONFIG_PCI_DEV_NUM	3U
+#define VM1_CONFIG_PCI_DEV_NUM	3U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+#define VM1_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/nuc7i7dnb.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/pci_dev.c

@@ -11,8 +11,16 @@
 #include <mmu.h>
 #include <page.h>
 
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
 #define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,
@@ -31,6 +39,10 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	},
 };
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,

misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/logical_partition/vm_configurations.c

@@ -10,12 +10,17 @@
 extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
 extern struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM];
 
+extern struct pt_intx_config vm0_pt_intx[1U];
+
 struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	{	/* VM0 */
 		CONFIG_PRE_STD_VM(1),
 		.name = "ACRN PRE-LAUNCHED VM0",
 		.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
 		.guest_flags = 0UL,
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM0_VCPU_CLOS,
+#endif
 		.memory = {
 			.start_hpa = VM0_CONFIG_MEM_START_HPA,
 			.size = VM0_CONFIG_MEM_SIZE,
@@ -26,9 +31,10 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 			.name = "YOCTO",
 			.kernel_type = KERNEL_BZIMAGE,
 			.kernel_mod_tag = "Linux_bzImage",
-			.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
+			.bootargs = VM0_BOOT_ARGS,
-				noxsave nohpet no_timer_check ignore_loglevel \
+		},
-				log_buf_len=16M consoleblank=0 tsc=reliable "
+		.acpi_config = {
+			.acpi_mod_tag = "ACPI_VM0",
 		},
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,
@@ -44,12 +50,33 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 		},
 		.pci_dev_num = VM0_CONFIG_PCI_DEV_NUM,
 		.pci_devs = vm0_pci_devs,
+#ifdef VM0_PASSTHROUGH_TPM
+		.pt_tpm2 = true,
+		.mmiodevs[0] = {
+			.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
+			.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
+			.size = VM0_TPM_BUFFER_SIZE,
+		},
+#endif
+#ifdef P2SB_BAR_ADDR
+		.pt_p2sb_bar = true,
+		.mmiodevs[0] = {
+			.base_gpa = P2SB_BAR_ADDR_GPA,
+			.base_hpa = P2SB_BAR_ADDR,
+			.size = P2SB_BAR_SIZE,
+		},
+#endif
+		.pt_intx_num = VM0_PT_INTX_NUM,
+		.pt_intx = &vm0_pt_intx[0U],
 	},
 	{	/* VM1 */
 		CONFIG_PRE_STD_VM(2),
 		.name = "ACRN PRE-LAUNCHED VM1",
 		.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
 		.guest_flags = 0UL,
+#ifdef CONFIG_RDT_ENABLED
+		.clos = VM1_VCPU_CLOS,
+#endif
 		.memory = {
 			.start_hpa = VM1_CONFIG_MEM_START_HPA,
 			.size = VM1_CONFIG_MEM_SIZE,
@@ -60,9 +87,10 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 			.name = "YOCTO",
 			.kernel_type = KERNEL_BZIMAGE,
 			.kernel_mod_tag = "Linux_bzImage",
-			.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
+			.bootargs = VM1_BOOT_ARGS,
-				noxsave nohpet no_timer_check ignore_loglevel \
+		},
-				log_buf_len=16M consoleblank=0 tsc=reliable "
+		.acpi_config = {
+			.acpi_mod_tag = "ACPI_VM1",
 		},
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,

misc/vm_configs/scenarios/logical_partition/vm_configurations.h

@@ -20,18 +20,14 @@
 
 #define DM_OWNED_GUEST_FLAG_MASK        0UL
 
-#define VM0_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
 #define VM0_CONFIG_MEM_START_HPA        0x100000000UL
 #define VM0_CONFIG_MEM_SIZE             0x20000000UL
 #define VM0_CONFIG_MEM_START_HPA2       0x0UL
 #define VM0_CONFIG_MEM_SIZE_HPA2        0x0UL
-#define VM0_CONFIG_PCI_DEV_NUM          3U
 
-#define VM1_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
 #define VM1_CONFIG_MEM_START_HPA        0x120000000UL
 #define VM1_CONFIG_MEM_SIZE             0x20000000UL
 #define VM1_CONFIG_MEM_START_HPA2       0x0UL
 #define VM1_CONFIG_MEM_SIZE_HPA2        0x0UL
-#define VM1_CONFIG_PCI_DEV_NUM          3U
 
 #endif /* VM_CONFIGURATIONS_H */

misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h

@@ -7,26 +7,32 @@
 #ifndef MISC_CFG_H
 #define MISC_CFG_H
 
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
+
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	3U
+#define VM1_CONFIG_PCI_DEV_NUM	3U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+#define VM1_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/pci_dev.c

@@ -11,8 +11,16 @@
 #include <mmu.h>
 #include <page.h>
 
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
 #define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,
@@ -31,6 +39,10 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	},
 };
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,

misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/whl-ipc-i5.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y

misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/ivshmem_cfg.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h

@@ -7,26 +7,32 @@
 #ifndef MISC_CFG_H
 #define MISC_CFG_H
 
+#define VM0_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
+#define VM1_CONFIG_CPU_AFFINITY	(AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
+
 #ifdef CONFIG_RDT_ENABLED
-/*
- * The maximum CLOS that is allowed by ACRN hypervisor,
- * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
- * among all supported RDT resources in the platform. In other words, it is
- * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
- * CLOS allocations between all the RDT resources.
- */
 #define HV_SUPPORTED_MAX_CLOS	0U
-
-/*
- * Max number of Cache Mask entries corresponding to each CLOS.
- * This can vary if CDP is enabled vs disabled, as each CLOS entry
- * will have corresponding cache mask values for Data and Code when
- * CDP is enabled.
- */
 #define MAX_MBA_CLOS_NUM_ENTRIES	0U
-
-/* Max number of MBA delay entries corresponding to each CLOS. */
 #define MAX_CACHE_CLOS_NUM_ENTRIES	0U
 #endif
 
+#define VM0_PASSTHROUGH_TPM
+#define VM0_TPM_BUFFER_BASE_ADDR   0xFED40000UL
+#define VM0_TPM_BUFFER_BASE_ADDR_GPA   0xFED40000UL
+#define VM0_TPM_BUFFER_SIZE        0x5000UL
+
+#define VM0_CONFIG_PCI_DEV_NUM	3U
+#define VM1_CONFIG_PCI_DEV_NUM	3U
+
+#define VM0_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+#define VM1_BOOT_ARGS	"rw rootwait root=/dev/sda3 console=ttyS0 \
+noxsave nohpet no_timer_check ignore_loglevel \
+log_buf_len=16M consoleblank=0 tsc=reliable"
+
+
+#define VM0_PT_INTX_NUM	0U
+
 #endif /* MISC_CFG_H */

misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/pci_dev.c

@@ -11,8 +11,16 @@
 #include <mmu.h>
 #include <page.h>
 
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
 #define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,
@@ -31,6 +39,10 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	},
 };
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,

misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/pt_intx.c

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <vm_config.h>
+
+struct pt_intx_config vm0_pt_intx[1U];
+

misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/whl-ipc-i7.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=n
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y