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hv: treewide: fix 'Macro parameter not in brackets'

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Add the brackets for Macro parameter to avoid the unintentional
mistakes.

A simple example that may cause mistakes:
        #define minus(x) -x
When the following call is made,
        z = minus(a-b)
it becomes:
        z = -a-b;
where "-a - b" is equivalent to "(-a) - b" rather than "- (a - b)", as
expected.

v2 -> v3:
 * convert DMAR_WAIT_COMPLETION to inline function
 * remove the macro PIC_PIN_FOREACH and implement the well-formed
   for loop in each case
 * replace __CPP_STRING with STRINGIFY and remove the unused CPP_STRING

v1 -> v2:
 * Remove some changes to function like macro since MISRA-C requires to
   use inline functions if it is possible.
   These MACRO brackets violations will be fixed together when fixing
   other issues related to function like macro.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This commit is contained in:
Shiqing Gao
2018-09-05 10:55:29 +08:00
committed by lijinxia
parent 30b77aba5d
commit 4360235edf
10 changed files with 92 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
hypervisor/include/arch/x86/cpu.h
View File

@@ -334,18 +334,18 @@ void stop_cpus(void);
void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
/* Read control register */
#define CPU_CR_READ(cr, result_ptr) \
{ \
asm volatile ("mov %%" __CPP_STRING(cr) ", %0" \
: "=r"(*result_ptr)); \
#define CPU_CR_READ(cr, result_ptr) \
{ \
asm volatile ("mov %%" STRINGIFY(cr) ", %0" \
: "=r"(*(result_ptr))); \
}
/* Write control register */
#define CPU_CR_WRITE(cr, value) \
{ \
asm volatile ("mov %0, %%" __CPP_STRING(cr) \
: /* No output */ \
: "r"(value)); \
#define CPU_CR_WRITE(cr, value) \
{ \
asm volatile ("mov %0, %%" STRINGIFY(cr) \
: /* No output */ \
: "r"(value)); \
}
/* Read MSR */

32
hypervisor/include/arch/x86/guest/guest.h
View File

@@ -18,10 +18,10 @@
#include <mmu.h>
#define foreach_vcpu(idx, vm, vcpu) \
for (idx = 0U, vcpu = vm->hw.vcpu_array[idx]; \
idx < vm->hw.num_vcpus; \
idx++, vcpu = vm->hw.vcpu_array[idx]) \
#define foreach_vcpu(idx, vm, vcpu) \
for ((idx) = 0U, vcpu = vm->hw.vcpu_array[(idx)]; \
(idx) < vm->hw.num_vcpus; \
(idx)++, vcpu = vm->hw.vcpu_array[(idx)]) \
if (vcpu != NULL)
/* the index is matched with emulated msrs array*/
@@ -46,20 +46,20 @@
#define E820_MAX_ENTRIES 32U
#define save_segment(seg, SEG_NAME) \
{ \
seg.selector = exec_vmread16(SEG_NAME##_SEL); \
seg.base = exec_vmread(SEG_NAME##_BASE); \
seg.limit = exec_vmread32(SEG_NAME##_LIMIT); \
seg.attr = exec_vmread32(SEG_NAME##_ATTR); \
#define save_segment(seg, SEG_NAME) \
{ \
(seg).selector = exec_vmread16(SEG_NAME##_SEL); \
(seg).base = exec_vmread(SEG_NAME##_BASE); \
(seg).limit = exec_vmread32(SEG_NAME##_LIMIT); \
(seg).attr = exec_vmread32(SEG_NAME##_ATTR); \
}
#define load_segment(seg, SEG_NAME) \
{ \
exec_vmwrite16(SEG_NAME##_SEL, seg.selector); \
exec_vmwrite(SEG_NAME##_BASE, seg.base); \
exec_vmwrite32(SEG_NAME##_LIMIT, seg.limit); \
exec_vmwrite32(SEG_NAME##_ATTR, seg.attr); \
#define load_segment(seg, SEG_NAME) \
{ \
exec_vmwrite16(SEG_NAME##_SEL, (seg).selector); \
exec_vmwrite(SEG_NAME##_BASE, (seg).base); \
exec_vmwrite32(SEG_NAME##_LIMIT, (seg).limit); \
exec_vmwrite32(SEG_NAME##_ATTR, (seg).attr); \
}
struct e820_mem_params {

2
hypervisor/include/arch/x86/per_cpu.h
View File

@@ -57,7 +57,7 @@ extern uint64_t pcpu_active_bitmap;
* get percpu data for pcpu_id.
*/
#define per_cpu(name, pcpu_id) \
(per_cpu_data_base_ptr[pcpu_id].name)
(per_cpu_data_base_ptr[(pcpu_id)].name)
/* get percpu data for current pcpu */
#define get_cpu_var(name) per_cpu(name, get_cpu_id())