hv: ensure PTM root is always enabled in hw

For post launch VM, ACRN supports PTM under these conditions:
1. HW implements a simple PTM hierarchy: PTM requestor device (ep) is
directly connected to PTM root capable root port. Or
2. ptm requestor itself is root complex integrated ep.
Currently acrn doesn't support emulation of other type of PTM hiearchy, such
as if there is an intermediate PTM node (for example, switch) inbetween
PTM requestor and PTM root.
To avoid VM touching physical hardware, acrn hv ensures PTM is always enabled
in the hardware.
During hv's pci init, if root port is ptm capable,
hv will enable PTM on that root port.  In addition,
log error (and don't enable PTM) if ptm root
capability is on intermediate node other than root port.

V2:
 - Modify commit messages to clarify the limitation
of current PTM implementation.
 - Fix code that may fail FUSA
 - Remove pci_ptm_info() and put info log inside pci_enable_ptm_root().

Tracked-On: #5915
Signed-off-by: Rong Liu <rong.l.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/include/hw/pci.h

@@ -136,8 +136,9 @@
 /* PTM Definitions */
 #define PCI_PTM_CAP_LEN				0x04U
 #define PCIR_PTM_CAP				0x04U
-#define PCIR_PTM_CTRL				0x08U
 #define PCIM_PTM_CAP_ROOT_CAPABLE	0x4U
+#define PCIM_PTM_GRANULARITY_MASK	0xFF00
+#define PCIR_PTM_CTRL				0x08U
 #define PCIM_PTM_CTRL_ENABLED		0x1U
 #define PCIM_PTM_CTRL_ROOT_SELECTED	0x2U
 
@@ -187,6 +188,13 @@
 #define PCIM_PCIE_FLRCAP      (0x1U << 28U)
 #define PCIM_PCIE_FLR         (0x1U << 15U)
 
+/* PCI Express Device Type definitions */
+#define PCIER_FLAGS                    0x2
+#define PCIEM_FLAGS_TYPE               0x00F0
+#define PCIEM_TYPE_ENDPOINT            0x0000
+#define PCIEM_TYPE_ROOTPORT            0x0004
+#define PCIEM_TYPE_ROOT_INT_EP         0x0009
+
 #define PCIR_PCIE_DEVCAP2     0x24U
 #define PCIM_PCIE_DEVCAP2_ARI (0x1U << 5U)
 #define PCIR_PCIE_DEVCTL2     0x28U