diff --git a/hypervisor/Makefile b/hypervisor/Makefile
index 91fda5a5f..29111f0e7 100644
--- a/hypervisor/Makefile
+++ b/hypervisor/Makefile
@@ -186,6 +186,7 @@ C_SRCS += arch/x86/guest/vmcs.c
 C_SRCS += arch/x86/guest/vmexit.c
 S_SRCS += arch/x86/guest/vmx_asm.S
 C_SRCS += arch/x86/guest/trusty.c
+C_SRCS += arch/x86/cat.c
 C_SRCS += lib/misc.c
 C_SRCS += lib/string.c
 C_SRCS += lib/memory.c
diff --git a/hypervisor/arch/x86/cat.c b/hypervisor/arch/x86/cat.c
new file mode 100644
index 000000000..64963fc62
--- /dev/null
+++ b/hypervisor/arch/x86/cat.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <types.h>
+#include <cpu.h>
+#include <cpu_caps.h>
+#include <cpufeatures.h>
+#include <cpuid.h>
+#include <msr.h>
+#include <errno.h>
+#include <logmsg.h>
+#include <cat.h>
+#include <board.h>
+
+struct cat_hw_info cat_cap_info;
+
+int32_t init_cat_cap_info(void)
+{
+	uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
+	int32_t ret = 0;
+
+	if (cpu_has_cap(X86_FEATURE_CAT)) {
+		cpuid_subleaf(CPUID_RSD_ALLOCATION, 0, &eax, &ebx, &ecx, &edx);
+		/* If support L3 CAT, EBX[1] is set */
+		if ((ebx & 2U) != 0U) {
+			cat_cap_info.res_id = CAT_RESID_L3;
+		}
+
+		/* If support L2 CAT, EBX[2] is set */
+		if ((ebx & 4U) != 0U) {
+			cat_cap_info.res_id = CAT_RESID_L2;
+		}
+
+		cat_cap_info.support = true;
+
+		/* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported
+		 * CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates the corresponding uints
+		 * may be used by other entities such as graphic and H/W outside processor.
+		 *  CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
+		 */
+		cpuid_subleaf(CPUID_RSD_ALLOCATION, cat_cap_info.res_id, &eax, &ebx, &ecx, &edx);
+		cat_cap_info.cbm_len = (uint16_t)((eax & 0xfU) + 1U);
+		cat_cap_info.bitmask = ebx;
+		cat_cap_info.clos_max = (uint16_t)(edx & 0xffffU);
+
+		if ((platform_clos_num != 0U) && ((cat_cap_info.clos_max + 1U) != platform_clos_num)) {
+			pr_err("%s clos_max:%hu, platform_clos_num:%u\n", __func__, cat_cap_info.clos_max, platform_clos_num);
+			ret = -EINVAL;
+		}
+	}
+
+	return ret;
+}
diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c
index f7a8dbbdd..86d252945 100644
--- a/hypervisor/arch/x86/cpu.c
+++ b/hypervisor/arch/x86/cpu.c
@@ -23,6 +23,7 @@
 #include <vm.h>
 #include <ld_sym.h>
 #include <logmsg.h>
+#include <cat.h>
 
 struct per_cpu_region per_cpu_data[CONFIG_MAX_PCPU_NUM] __aligned(PAGE_SIZE);
 static uint16_t phys_cpu_num = 0U;
@@ -130,6 +131,12 @@ void init_cpu_pre(uint16_t pcpu_id_args)
 		if (ret != 0) {
 			panic("System IOAPIC info is incorrect!");
 		}
+
+		ret = init_cat_cap_info();
+		if (ret != 0) {
+			panic("Platform CAT info is incorrect!");
+		}
+
 	} else {
 		/* Switch this CPU to use the same page tables set-up by the
 		 * primary/boot CPU
diff --git a/hypervisor/include/arch/x86/cat.h b/hypervisor/include/arch/x86/cat.h
new file mode 100644
index 000000000..1739a07a4
--- /dev/null
+++ b/hypervisor/include/arch/x86/cat.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CAT_H
+#define CAT_H
+
+/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
+struct cat_hw_info {
+	bool support;		/* If L2/L3 CAT supported */
+	bool enabled;		/* If any VM setup CLOS */
+	uint32_t bitmask;	/* Used by other entities */
+	uint16_t cbm_len;	/* Length of Cache mask in bits */
+	uint16_t clos_max;	/* Maximum CLOS supported, the number of cache masks */
+
+	uint32_t res_id;
+};
+
+extern struct cat_hw_info cat_cap_info;
+
+#define CAT_RESID_L3   1U
+#define CAT_RESID_L2   2U
+
+int32_t init_cat_cap_info(void);
+
+#endif	/* CAT_H */
diff --git a/hypervisor/include/arch/x86/cpufeatures.h b/hypervisor/include/arch/x86/cpufeatures.h
index c00cca9db..af41ba766 100644
--- a/hypervisor/include/arch/x86/cpufeatures.h
+++ b/hypervisor/include/arch/x86/cpufeatures.h
@@ -73,6 +73,7 @@
 #define X86_FEATURE_SMEP	((FEAT_7_0_EBX << 5U) +  7U)
 #define X86_FEATURE_ERMS	((FEAT_7_0_EBX << 5U) +  9U)
 #define X86_FEATURE_INVPCID	((FEAT_7_0_EBX << 5U) + 10U)
+#define X86_FEATURE_CAT        ((FEAT_7_0_EBX << 5U) + 15U)
 #define X86_FEATURE_SMAP	((FEAT_7_0_EBX << 5U) + 20U)
 
 /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
diff --git a/hypervisor/include/arch/x86/cpuid.h b/hypervisor/include/arch/x86/cpuid.h
index 76a23c13c..e898d6dd8 100644
--- a/hypervisor/include/arch/x86/cpuid.h
+++ b/hypervisor/include/arch/x86/cpuid.h
@@ -100,6 +100,7 @@
 #define CPUID_TLB               2U
 #define CPUID_SERIALNUM         3U
 #define CPUID_EXTEND_FEATURE    7U
+#define CPUID_RSD_ALLOCATION   0x10U
 #define CPUID_MAX_EXTENDED_FUNCTION  0x80000000U
 #define CPUID_EXTEND_FUNCTION_1      0x80000001U
 #define CPUID_EXTEND_FUNCTION_2      0x80000002U