github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-19 04:02:05 +00:00
Code Issues Projects Releases Wiki Activity

hv: keylocker: Enable the tertiary VM-execution controls

Browse Source 
In order for a VMM to capture the IWKey values of guests, processors
that support Key Locker also support a new "LOADIWKEY exiting"
VM-execution control in bit 0 of the tertiary processor-based
VM-execution controls.

This patch enables the tertiary VM-execution controls.

Tracked-On: #5695
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shuo A Liu 2020-08-24 20:00:28 +08:00 committed by wenlingz
parent e9247dbca0
commit 4483e93bd1
3 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hypervisor/arch/x86/guest/vmcs.c
View File

@ -266,6 +266,7 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
* guest access to IO bit-mapped ports causes VM exit
* guest access to MSR causes VM exit
* Activate secondary controls
* Activate tertiary controls
*/
/* These are bits 1,4-6,8,13-16, and 26, the corresponding bits of
* the IA32_VMX_PROCBASED_CTRLS MSR are always read as 1 --- A.3.2
@ -273,7 +274,7 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
value32 = check_vmx_ctrl(MSR_IA32_VMX_PROCBASED_CTLS,
VMX_PROCBASED_CTLS_TSC_OFF | VMX_PROCBASED_CTLS_TPR_SHADOW |
VMX_PROCBASED_CTLS_IO_BITMAP | VMX_PROCBASED_CTLS_MSR_BITMAP |
VMX_PROCBASED_CTLS_HLT | VMX_PROCBASED_CTLS_SECONDARY);
VMX_PROCBASED_CTLS_HLT | VMX_PROCBASED_CTLS_SECONDARY | VMX_PROCBASED_CTLS_TERTIARY);
/*Disable VM_EXIT for CR3 access*/
value32 &= ~(VMX_PROCBASED_CTLS_CR3_LOAD | VMX_PROCBASED_CTLS_CR3_STORE);

1
hypervisor/include/arch/x86/msr.h
View File

@ -254,6 +254,7 @@
#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048FU
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490U
#define MSR_IA32_VMX_VMFUNC 0x00000491U
#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492U
#define MSR_IA32_A_PMC0 0x000004C1U
#define MSR_IA32_A_PMC1 0x000004C2U
#define MSR_IA32_A_PMC2 0x000004C3U

1
hypervisor/include/arch/x86/vmx.h
View File

@ -281,6 +281,7 @@
#define VMX_PROCBASED_CTLS_RDTSC (1U<<12U)
#define VMX_PROCBASED_CTLS_CR3_LOAD (1U<<15U)
#define VMX_PROCBASED_CTLS_CR3_STORE (1U<<16U)
#define VMX_PROCBASED_CTLS_TERTIARY (1U<<17U)
#define VMX_PROCBASED_CTLS_CR8_LOAD (1U<<19U)
#define VMX_PROCBASED_CTLS_CR8_STORE (1U<<20U)
#define VMX_PROCBASED_CTLS_TPR_SHADOW (1U<<21U)