hv: fix 'User name starts with underscore'

There are chances that names with leading underscore declared by
developers are conflict with the ones reserved for the compiler.

What this patch does:
- rename these functions/variables/macros starting with
  underscore to avoid such unintentational mistakes.
- remove gpr.h without any contents

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
2018-09-29 15:46:27 +08:00
committed by Xie, Nanlin
parent 390861a04c
commit 4544d28ee1
27 changed files with 75 additions and 95 deletions

View File

@@ -26,8 +26,8 @@
* $FreeBSD$
*/
#ifndef _APICREG_H_
#define _APICREG_H_
#ifndef APICREG_H
#define APICREG_H
/*
* Local && I/O APIC definitions.
@@ -432,4 +432,4 @@ union ioapic_rte {
#define IOAPIC_RTE_INTVEC 0x000000ffUL /*R/W: INT vector field*/
#endif /* _APICREG_H_ */
#endif /* APICREG_H */

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@@ -216,8 +216,8 @@ enum cpu_reg_name {
/**********************************/
/* EXTERNAL VARIABLES */
/**********************************/
extern uint8_t _ld_bss_start;
extern uint8_t _ld_bss_end;
extern uint8_t ld_bss_start;
extern uint8_t ld_bss_end;
/* In trampoline range, hold the jump target which trampline will jump to */
extern uint64_t main_entry[1];

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@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __X86_CPUFEATURES_H__
#define __X86_CPUFEATURES_H__
#ifndef CPUFEATURES_H
#define CPUFEATURES_H
/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5U) + 0U)
@@ -83,4 +83,4 @@
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U)
#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U)
#endif /*__X86_CPUFEATURES_H__*/
#endif /* CPUFEATURES_H */

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@@ -1,10 +0,0 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _VGPR_H_
#define _VGPR_H_
#endif

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@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ARCH_X86_UCODE_H
#define _ARCH_X86_UCODE_H
#ifndef UCODE_H
#define UCODE_H
struct ucode_header {
uint32_t header_ver;
@@ -23,4 +23,4 @@ struct ucode_header {
void acrn_update_ucode(struct vcpu *vcpu, uint64_t v);
uint64_t get_microcode_version(void);
#endif
#endif /* UCODE_H */

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@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _VCPU_H_
#define _VCPU_H_
#ifndef VCPU_H
#define VCPU_H
#define ACRN_VCPU_MMIO_COMPLETE (0U)
@@ -47,7 +47,6 @@
#ifndef ASSEMBLER
#include <guest.h>
#include <gpr.h>
enum vcpu_state {
VCPU_INIT,
@@ -239,7 +238,7 @@ struct vcpu {
uint64_t guest_msrs[IDX_MAX_MSR];
#ifdef CONFIG_MTRR_ENABLED
struct mtrr_state mtrr;
#endif
#endif /* CONFIG_MTRR_ENABLED */
uint64_t reg_cached;
uint64_t reg_updated;
} __aligned(CPU_PAGE_SIZE);
@@ -303,6 +302,6 @@ int prepare_vcpu(struct vm *vm, uint16_t pcpu_id);
void request_vcpu_pre_work(struct vcpu *vcpu, uint16_t pre_work_id);
void vcpu_dumpreg(void *data);
#endif
#endif /* ASSEMBLER */
#endif
#endif /* VCPU_H */

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@@ -28,8 +28,8 @@
* $FreeBSD$
*/
#ifndef _VIOAPIC_H_
#define _VIOAPIC_H_
#ifndef VIOAPIC_H
#define VIOAPIC_H
#include <apicreg.h>
@@ -65,4 +65,4 @@ int vioapic_mmio_access_handler(struct vcpu *vcpu,
void get_vioapic_info(char *str_arg, size_t str_max, uint16_t vmid);
#endif /* HV_DEBUG */
#endif
#endif /* VIOAPIC_H */

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@@ -27,8 +27,8 @@
* $FreeBSD$
*/
#ifndef _VLAPIC_H_
#define _VLAPIC_H_
#ifndef VLAPIC_H
#define VLAPIC_H
/*
* 16 priority levels with at most one vector injected per level.
@@ -186,4 +186,4 @@ int apic_write_vmexit_handler(struct vcpu *vcpu);
int veoi_vmexit_handler(struct vcpu *vcpu);
int tpr_below_threshold_vmexit_handler(__unused struct vcpu *vcpu);
void calcvdest(struct vm *vm, uint64_t *dmask, uint32_t dest, bool phys);
#endif /* _VLAPIC_H_ */
#endif /* VLAPIC_H */

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@@ -146,13 +146,6 @@ struct vm {
* when vm is active. So no lock needed
*/
struct _vm_shared_memory *shared_memory_area;
struct {
struct _vm_virtual_device_node *head;
struct _vm_virtual_device_node *tail;
} virtual_device_list;
unsigned char GUID[16];
struct secure_world_control sworld_control;

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@@ -26,7 +26,6 @@
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#include <gpr.h>
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U

View File

@@ -27,8 +27,8 @@
* $FreeBSD$
*/
#ifndef _VPIC_H_
#define _VPIC_H_
#ifndef VPIC_H
#define VPIC_H
#define ICU_IMR_OFFSET 1U
@@ -129,4 +129,4 @@ void vpic_get_irq_trigger(struct vm *vm, uint32_t irq,
enum vpic_trigger *trigger);
uint32_t vpic_pincount(void);
#endif /* _VPIC_H_ */
#endif /* VPIC_H */

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@@ -11,10 +11,9 @@
extern uint8_t host_enter_s3_success;
int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val);
extern void __enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
extern void asm_enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val);
extern void restore_s3_context(void);
#endif /* ARCH_X86_PM_H */
#endif /* HOST_PM_H */