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dm: e820: refine e820 layout

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We don't reserve PCI MMIO in e820 Table, it's included in DSDT ACPI Table.
About 0xA0000 - 0x100000 entry, we don't have any ACPI Table touch this region.
So we could remove it too.

After this change, we could only pass the reserved e820 table which we must
reserve to OVMF. In this case, the OVMF could trust ACRN-DM and pass the
reserved e820 table to guest instead of dropping it.

This patch needs the corresponding modify in OVMF. Otherwise, the guest could
not boot.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Li Fei1
2020-10-20 15:28:55 +08:00
committed by Fuzhong Liu
parent bb6b226c86
commit 460124f984
6 changed files with 27 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
devicemodel/include/pci_core.h
View File

@@ -40,6 +40,9 @@
#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
#define PCI_BDF(b, d, f) (((b & 0xFF) << 8) | ((d & 0x1F) << 3) | ((f & 0x7)))
#define PCI_EMUL_MEMBASE32 0x80000000UL /* 2GB */
#define PCI_EMUL_MEMLIMIT32 0xC0000000UL /* 3GB */
#define PCI_EMUL_ECFG_BASE 0xE0000000UL /* 3.5GB */
#define PCI_EMUL_MEMBASE64 0x100000000UL /* 4GB */

6
devicemodel/include/sw_load.h
View File

@@ -39,9 +39,9 @@
#define E820_TYPE_ACPI_NVS 4U /* EFI 10 */
#define E820_TYPE_UNUSABLE 5U /* EFI 8 */
#define NUM_E820_ENTRIES 10
#define LOWRAM_E820_ENTRY 2
#define HIGHRAM_E820_ENTRY 9
#define NUM_E820_ENTRIES 5
#define LOWRAM_E820_ENTRY 1
#define HIGHRAM_E820_ENTRY 4
/* Defines a single entry in an E820 memory map. */
struct e820_entry {