mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-09-21 00:38:28 +00:00
hv: vioapic init for SOS VM on platforms with multiple IO-APICs
For SOS VM, when the target platform has multiple IO-APICs, there should be equal number of virtual IO-APICs. This patch adds support for emulating multiple vIOAPICs per VM. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Sainath Grandhi
committed by
wenlingz
wenlingz
parent
f3cf93656a
commit
4626c9154f
@@ -36,6 +36,7 @@
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#include <ept.h>
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#include <assign.h>
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#include <logmsg.h>
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#include <ioapic.h>
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#define RTBL_RO_BITS ((uint32_t)0x00004000U | (uint32_t)0x00001000U) /*Remote IRR and Delivery Status bits*/
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@@ -45,16 +46,16 @@
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#define IOAPIC_ID_MASK 0x0f000000U
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#define MASK_ALL_INTERRUPTS 0x0001000000010000UL
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static inline struct acrn_vioapic *vm_ioapic(const struct acrn_vm *vm)
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static inline struct acrn_vioapics *vm_ioapics(const struct acrn_vm *vm)
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{
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return (struct acrn_vioapic *)&(vm->arch_vm.vioapic);
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return (struct acrn_vioapics *)&(vm->arch_vm.vioapics);
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}
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/**
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* @pre pin < vioapic_pincount(vm)
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* @pre pin < vioapic->nr_pins
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*/
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static void
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vioapic_generate_intr(struct acrn_vioapic *vioapic, uint32_t pin)
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vioapic_generate_intr(struct acrn_single_vioapic *vioapic, uint32_t pin)
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{
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uint32_t vector, dest, delmode;
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union ioapic_rte rte;
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@@ -84,10 +85,10 @@ vioapic_generate_intr(struct acrn_vioapic *vioapic, uint32_t pin)
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}
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/**
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* @pre pin < vioapic_pincount(vm)
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* @pre pin < vioapic->nr_pins
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*/
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static void
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vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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vioapic_set_pinstate(struct acrn_single_vioapic *vioapic, uint32_t pin, uint32_t level)
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{
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uint32_t old_lvl;
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union ioapic_rte rte;
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@@ -113,6 +114,30 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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}
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}
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static struct acrn_single_vioapic *
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vgsi_to_vioapic_and_vpin(const struct acrn_vm *vm, uint32_t vgsi, uint32_t *vpin)
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{
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struct acrn_single_vioapic *vioapic;
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uint8_t vioapic_index = 0U;
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if (is_sos_vm(vm)) {
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/*
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* Utilize platform ioapic_info for SOS VM
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*/
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vioapic_index = get_gsi_to_ioapic_index(vgsi);
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if (vpin != NULL) {
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*vpin = gsi_to_ioapic_pin(vgsi);
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}
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} else {
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if (vpin != NULL) {
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*vpin = vgsi;
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}
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}
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vioapic = (struct acrn_single_vioapic *)&(vm->arch_vm.vioapics.vioapic_array[vioapic_index]);
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return vioapic;
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}
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/**
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* @brief Set vIOAPIC IRQ line status.
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*
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@@ -120,11 +145,11 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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* operation be done with ioapic lock.
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*
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* @param[in] vm Pointer to target VM
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* @param[in] irqline Target IRQ number
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* @param[in] vgsi Target GSI number
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* @param[in] operation Action options: GSI_SET_HIGH/GSI_SET_LOW/
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* GSI_RAISING_PULSE/GSI_FALLING_PULSE
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*
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* @pre irqline < vioapic_pincount(vm)
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* @pre vgsi < get_vm_gsicount(vm)
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* @pre vm != NULL
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* @pre vioapic->ready == true
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* @return None
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@@ -132,10 +157,10 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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void
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vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t operation)
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{
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struct acrn_vioapic *vioapic;
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uint32_t pin = vgsi;
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struct acrn_single_vioapic *vioapic;
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uint32_t pin;
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vioapic = vm_ioapic(vm);
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vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, &pin);
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switch (operation) {
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case GSI_SET_HIGH:
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@@ -164,11 +189,11 @@ vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t ope
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* @brief Set vIOAPIC IRQ line status.
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*
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* @param[in] vm Pointer to target VM
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* @param[in] irqline Target IRQ number
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* @param[in] vgsi Target GSI number
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* @param[in] operation Action options: GSI_SET_HIGH/GSI_SET_LOW/
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* GSI_RAISING_PULSE/GSI_FALLING_PULSE
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*
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* @pre irqline < vioapic_pincount(vm)
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* @pre vgsi < get_vm_gsicount(vm)
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* @pre vm != NULL
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*
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* @return None
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@@ -177,20 +202,21 @@ void
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vioapic_set_irqline_lock(const struct acrn_vm *vm, uint32_t vgsi, uint32_t operation)
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{
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uint64_t rflags;
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uint32_t irqline = vgsi;
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struct acrn_vioapic *vioapic = vm_ioapic(vm);
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struct acrn_single_vioapic *vioapic;
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vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, NULL);
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if (vioapic->ready) {
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spinlock_irqsave_obtain(&(vioapic->mtx), &rflags);
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vioapic_set_irqline_nolock(vm, irqline, operation);
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vioapic_set_irqline_nolock(vm, vgsi, operation);
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spinlock_irqrestore_release(&(vioapic->mtx), rflags);
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}
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}
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static uint32_t
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vioapic_indirect_read(const struct acrn_vioapic *vioapic, uint32_t addr)
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vioapic_indirect_read(const struct acrn_single_vioapic *vioapic, uint32_t addr)
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{
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uint32_t regnum, ret = 0U;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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regnum = addr & 0xffU;
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switch (regnum) {
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@@ -229,7 +255,7 @@ vioapic_indirect_read(const struct acrn_vioapic *vioapic, uint32_t addr)
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return ret;
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}
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static inline bool vioapic_need_intr(const struct acrn_vioapic *vioapic, uint16_t pin)
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static inline bool vioapic_need_intr(const struct acrn_single_vioapic *vioapic, uint16_t pin)
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{
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uint32_t lvl;
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union ioapic_rte rte;
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@@ -250,11 +276,11 @@ static inline bool vioapic_need_intr(const struct acrn_vioapic *vioapic, uint16_
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* spinlock_irqsave_obtain(&(vioapic->mtx), &rflags) & spinlock_irqrestore_release(&(vioapic->mtx), rflags)
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* by caller.
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*/
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static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr, uint32_t data)
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static void vioapic_indirect_write(struct acrn_single_vioapic *vioapic, uint32_t addr, uint32_t data)
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{
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union ioapic_rte last, new, changed;
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uint32_t regnum;
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uint32_t pin, pincount = vioapic_pincount(vioapic->vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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regnum = addr & 0xffUL;
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switch (regnum) {
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@@ -332,7 +358,8 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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if ((new.bits.intr_mask == IOAPIC_RTE_MASK_CLR) || (last.bits.intr_mask == IOAPIC_RTE_MASK_CLR)) {
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/* VM enable intr */
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/* NOTE: only support max 256 pin */
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(void)ptirq_intx_pin_remap(vioapic->vm, pin, INTX_CTLR_IOAPIC);
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(void)ptirq_intx_pin_remap(vioapic->vm, vioapic->gsi_base + pin, INTX_CTLR_IOAPIC);
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}
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/*
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@@ -352,7 +379,7 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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}
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static void
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vioapic_mmio_rw(struct acrn_vioapic *vioapic, uint64_t gpa,
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vioapic_mmio_rw(struct acrn_single_vioapic *vioapic, uint64_t gpa,
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uint32_t *data, bool do_read)
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{
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uint32_t offset;
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@@ -396,11 +423,10 @@ vioapic_mmio_rw(struct acrn_vioapic *vioapic, uint64_t gpa,
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* @pre vm != NULL
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* @pre vioapic->ready == true
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*/
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void
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vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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static void
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vioapic_process_eoi(struct acrn_single_vioapic *vioapic, uint32_t vector)
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{
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struct acrn_vioapic *vioapic;
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uint32_t pin, pincount = vioapic_pincount(vm);
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uint32_t pin, pincount = vioapic->nr_pins;
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union ioapic_rte rte;
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uint64_t rflags;
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@@ -408,7 +434,6 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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pr_err("vioapic_process_eoi: invalid vector %u", vector);
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}
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vioapic = vm_ioapic(vm);
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dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic processing eoi for vector %u", vector);
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/* notify device to ack if assigned pin */
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@@ -419,7 +444,7 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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continue;
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}
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ptirq_intx_ack(vm, pin, INTX_CTLR_IOAPIC);
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ptirq_intx_ack(vioapic->vm, vioapic->gsi_base + pin, INTX_CTLR_IOAPIC);
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}
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/*
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@@ -444,14 +469,28 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
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spinlock_irqrestore_release(&(vioapic->mtx), rflags);
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}
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void
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vioapic_reset(struct acrn_vm *vm)
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void vioapic_broadcast_eoi(const struct acrn_vm *vm, uint32_t vector)
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{
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struct acrn_single_vioapic *vioapic;
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uint8_t vioapic_index;
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/*
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* For platforms with multiple IO-APICs, EOI message from LAPIC is
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* broadcast to all IO-APICs. Emulating the same behavior here.
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*/
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for (vioapic_index = 0U; vioapic_index < vm->arch_vm.vioapics.ioapic_num; vioapic_index++) {
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vioapic = &(vm_ioapics(vm)->vioapic_array[vioapic_index]);
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vioapic_process_eoi(vioapic, vector);
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}
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}
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static void reset_one_vioapic(struct acrn_single_vioapic *vioapic)
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{
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uint32_t pin, pincount;
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struct acrn_vioapic *vioapic = vm_ioapic(vm);
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/* Initialize all redirection entries to mask all interrupts */
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pincount = vioapic_pincount(vm);
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pincount = vioapic->nr_pins;
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for (pin = 0U; pin < pincount; pin++) {
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vioapic->rtbl[pin].full = MASK_ALL_INTERRUPTS;
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}
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@@ -459,35 +498,80 @@ vioapic_reset(struct acrn_vm *vm)
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vioapic->ioregsel = 0U;
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}
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void reset_vioapics(const struct acrn_vm *vm)
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{
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struct acrn_vioapics *vioapics = vm_ioapics(vm);
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uint8_t vioapic_index;
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for (vioapic_index = 0U; vioapic_index < vioapics->ioapic_num; vioapic_index++) {
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reset_one_vioapic(&vioapics->vioapic_array[vioapic_index]);
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}
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}
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void
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vioapic_init(struct acrn_vm *vm)
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{
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vm->arch_vm.vioapic.vm = vm;
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spinlock_init(&(vm->arch_vm.vioapic.mtx));
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struct ioapic_info *platform_ioapic_info;
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uint8_t platform_ioapic_num;
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uint8_t vioapic_index;
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struct acrn_single_vioapic *vioapic;
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vm->arch_vm.vioapic.base_addr = VIOAPIC_BASE;
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if (is_sos_vm(vm)) {
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vm->arch_vm.vioapic.nr_pins = REDIR_ENTRIES_HW;
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platform_ioapic_num = get_platform_ioapic_info(&platform_ioapic_info);
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vm->arch_vm.vioapics.ioapic_num = platform_ioapic_num;
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for (vioapic_index = 0U; vioapic_index < platform_ioapic_num; vioapic_index++) {
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vioapic = &vm->arch_vm.vioapics.vioapic_array[vioapic_index];
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spinlock_init(&(vioapic->mtx));
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vioapic->nr_pins = platform_ioapic_info[vioapic_index].nr_pins;
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vioapic->base_addr = platform_ioapic_info[vioapic_index].addr;
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vioapic->gsi_base = platform_ioapic_info[vioapic_index].gsi_base;
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vioapic->vm = vm;
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reset_one_vioapic(vioapic);
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register_mmio_emulation_handler(vm,
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vioapic_mmio_access_handler,
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(uint64_t)vioapic->base_addr,
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(uint64_t)vioapic->base_addr + VIOAPIC_SIZE,
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(void *)vioapic, false);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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(uint64_t)vioapic->base_addr, VIOAPIC_SIZE);
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vioapic->ready = true;
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}
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/*
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* Maximum number of GSI is computed as GSI base of the IOAPIC i.e. enumerated last in ACPI MADT
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* plus the number of interrupt pins of that IOAPIC.
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*/
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vm->arch_vm.vioapics.nr_gsi = platform_ioapic_info[platform_ioapic_num - 1U].gsi_base +
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platform_ioapic_info[platform_ioapic_num - 1U].nr_pins;
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} else {
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vm->arch_vm.vioapic.nr_pins = VIOAPIC_RTE_NUM;
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vm->arch_vm.vioapics.ioapic_num = 1U;
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vioapic = &vm->arch_vm.vioapics.vioapic_array[0U];
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spinlock_init(&(vioapic->mtx));
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vioapic->nr_pins = VIOAPIC_RTE_NUM;
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vioapic->base_addr = VIOAPIC_BASE;
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vioapic->gsi_base = 0U;
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vioapic->vm = vm;
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reset_one_vioapic(&vm->arch_vm.vioapics.vioapic_array[0U]);
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register_mmio_emulation_handler(vm,
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vioapic_mmio_access_handler,
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(uint64_t)vioapic->base_addr,
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(uint64_t)vioapic->base_addr + VIOAPIC_SIZE,
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(void *)vioapic, false);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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(uint64_t)vioapic->base_addr, VIOAPIC_SIZE);
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vioapic->ready = true;
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vm->arch_vm.vioapics.nr_gsi = VIOAPIC_RTE_NUM;
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}
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vioapic_reset(vm);
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register_mmio_emulation_handler(vm,
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vioapic_mmio_access_handler,
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(uint64_t)vm->arch_vm.vioapic.base_addr,
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(uint64_t)vm->arch_vm.vioapic.base_addr + VIOAPIC_SIZE,
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(void *)&vm->arch_vm.vioapic, false);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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(uint64_t)vm->arch_vm.vioapic.base_addr, VIOAPIC_SIZE);
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vm->arch_vm.vioapic.ready = true;
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}
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uint32_t
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vioapic_pincount(const struct acrn_vm *vm)
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get_vm_gsicount(const struct acrn_vm *vm)
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{
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return vm->arch_vm.vioapic.nr_pins;
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return vm->arch_vm.vioapics.nr_gsi;
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}
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/*
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@@ -496,7 +580,7 @@ vioapic_pincount(const struct acrn_vm *vm)
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*/
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int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_private_data)
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{
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struct acrn_vioapic *vioapic = (struct acrn_vioapic *)handler_private_data;
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struct acrn_single_vioapic *vioapic = (struct acrn_single_vioapic *)handler_private_data;
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struct mmio_request *mmio = &io_req->reqs.mmio;
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uint64_t gpa = mmio->address;
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int32_t ret = 0;
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@@ -522,14 +606,15 @@ int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_pri
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}
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/**
|
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* @pre vm->arch_vm.vioapic != NULL
|
||||
* @pre vm->arch_vm.vioapics != NULL
|
||||
* @pre vgsi < get_vm_gsicount(vm)
|
||||
* @pre rte != NULL
|
||||
*/
|
||||
void vioapic_get_rte(const struct acrn_vm *vm, uint32_t vgsi, union ioapic_rte *rte)
|
||||
{
|
||||
struct acrn_vioapic *vioapic;
|
||||
uint32_t pin = vgsi;
|
||||
struct acrn_single_vioapic *vioapic;
|
||||
uint32_t pin;
|
||||
vioapic = vgsi_to_vioapic_and_vpin(vm, vgsi, &pin);
|
||||
|
||||
vioapic = vm_ioapic(vm);
|
||||
*rte = vioapic->rtbl[pin];
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user