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hv: pci_priv.h code cleanup

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- move most of the content of pci_priv.h to include/dm/pci.h.
  This allows other code outside dm/vpci to be able to share these macros.
- code cleanup: fix alignments etc.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen 2018-09-19 22:47:01 -07:00 committed by Xie, Nanlin
parent a43ff9ce98
commit 4741fcfff2
3 changed files with 76 additions and 43 deletions
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1
hypervisor/Makefile
View File

@ -101,6 +101,7 @@ INCLUDE_PATH += include/debug
INCLUDE_PATH += include/public INCLUDE_PATH += include/public
ifeq ($(CONFIG_PARTITION_MODE),y) ifeq ($(CONFIG_PARTITION_MODE),y)
INCLUDE_PATH += include/dm/vpci INCLUDE_PATH += include/dm/vpci
INCLUDE_PATH += include/dm
endif endif
INCLUDE_PATH += bsp/include INCLUDE_PATH += bsp/include
INCLUDE_PATH += bsp/include/$(CONFIG_PLATFORM) INCLUDE_PATH += bsp/include/$(CONFIG_PLATFORM)

46
hypervisor/dm/vpci/pci_priv.h
View File

@ -30,35 +30,7 @@
#ifndef PCI_PRIV_H_ #ifndef PCI_PRIV_H_
#define PCI_PRIV_H_ #define PCI_PRIV_H_
#include <hv_debug.h> #include <pci.h>
#include "vpci.h"
#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
#define PCI_BUSMAX 0xFFU
#define PCI_SLOTMAX 0x1FU
#define PCI_FUNCMAX 0x7U
#define PCIR_VENDOR 0x00U
#define PCIR_DEVICE 0x02U
#define PCIR_COMMAND 0x04U
#define PCIR_REVID 0x08U
#define PCIR_SUBCLASS 0x0AU
#define PCIR_CLASS 0x0BU
#define PCIR_HDRTYPE 0x0EU
#define PCIM_HDRTYPE_NORMAL 0x00U
#define PCIM_MFDEV 0x80U
#define PCIC_BRIDGE 0x06U
#define PCIS_BRIDGE_HOST 0x00U
#define PCI_CONFIG_ADDR 0xCF8U
#define PCI_CONFIG_DATA 0xCFCU
#define PCI_CFG_ENABLE 0x80000000U
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
static inline uint8_t static inline uint8_t
pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset) pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
@ -132,19 +104,7 @@ static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
} }
} }
static inline uint32_t pci_bar_offset(uint32_t idx) void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
{ union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
return 0x10U + (idx << 2U);
}
static inline int pci_bar_access(uint32_t offset)
{
if ((offset >= pci_bar_offset(0U))
&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
return 1;
} else {
return 0;
}
}
#endif /* PCI_PRIV_H_ */ #endif /* PCI_PRIV_H_ */

72
hypervisor/include/dm/pci.h Normal file
View File

@ -0,0 +1,72 @@
/*-
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2018 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef PCI_H_
#define PCI_H_
#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
#define PCI_BUSMAX 0xFFU
#define PCI_SLOTMAX 0x1FU
#define PCI_FUNCMAX 0x7U
#define PCIR_VENDOR 0x00U
#define PCIR_DEVICE 0x02U
#define PCIR_COMMAND 0x04U
#define PCIR_REVID 0x08U
#define PCIR_SUBCLASS 0x0AU
#define PCIR_CLASS 0x0BU
#define PCIR_HDRTYPE 0x0EU
#define PCIM_HDRTYPE_NORMAL 0x00U
#define PCIM_MFDEV 0x80U
#define PCIC_BRIDGE 0x06U
#define PCIS_BRIDGE_HOST 0x00U
#define PCI_CONFIG_ADDR 0xCF8U
#define PCI_CONFIG_DATA 0xCFCU
#define PCI_CFG_ENABLE 0x80000000U
static inline uint32_t pci_bar_offset(uint32_t idx)
{
return 0x10U + (idx << 2U);
}
static inline int pci_bar_access(uint32_t offset)
{
if ((offset >= pci_bar_offset(0U))
&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
return 1;
} else {
return 0;
}
}
#endif /* PCI_H_ */