diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c index cd4b55b56..472250e4d 100644 --- a/hypervisor/arch/x86/cpu.c +++ b/hypervisor/arch/x86/cpu.c @@ -28,7 +28,7 @@ uint64_t pcpu_sync = 0UL; volatile uint16_t up_count = 0U; /* physical cpu active bitmap, support up to 64 cpus */ -uint64_t pcpu_active_bitmap = 0; +uint64_t pcpu_active_bitmap = 0UL; uint64_t trampoline_start16_paddr; @@ -77,7 +77,7 @@ inline bool cpu_has_cap(uint32_t bit) if (feat_idx >= FEATURE_WORDS) return false; - return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit)) != 0U); + return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1U << feat_bit)) != 0U); } static inline bool get_monitor_cap(void) @@ -111,15 +111,15 @@ static void get_cpu_capabilities(void) cpuid(CPUID_FEATURES, &eax, &unused, &boot_cpu_data.cpuid_leaves[FEAT_1_ECX], &boot_cpu_data.cpuid_leaves[FEAT_1_EDX]); - family = (eax >> 8) & 0xffU; + family = (eax >> 8U) & 0xffU; if (family == 0xFU) - family += (eax >> 20) & 0xffU; + family += (eax >> 20U) & 0xffU; boot_cpu_data.x86 = family; - model = (eax >> 4) & 0xfU; + model = (eax >> 4U) & 0xfU; if (family >= 0x06U) - model += ((eax >> 16) & 0xfU) << 4; - boot_cpu_data.x86_model = model; + model += ((eax >> 16U) & 0xfU) << 4U; + boot_cpu_data.x86_model = (uint8_t)model; cpuid(CPUID_EXTEND_FEATURE, &unused, @@ -144,8 +144,8 @@ static void get_cpu_capabilities(void) /* EAX bits 07-00: #Physical Address Bits * bits 15-08: #Linear Address Bits */ - boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xffU; - boot_cpu_data.x86_phys_bits = eax & 0xffU; + boot_cpu_data.x86_virt_bits = (uint8_t)((eax >> 8U) & 0xffU); + boot_cpu_data.x86_phys_bits = (uint8_t)(eax & 0xffU); boot_cpu_data.physical_address_mask = get_address_mask(boot_cpu_data.x86_phys_bits); } @@ -317,7 +317,7 @@ static void cpu_set_current_state(uint16_t pcpu_id, enum cpu_state state) #ifdef STACK_PROTECTOR static uint64_t get_random_value(void) { - uint64_t random = 0; + uint64_t random = 0UL; asm volatile ("1: rdrand %%rax\n" "jnc 1b\n" @@ -374,7 +374,7 @@ void bsp_boot_init(void) * is matching the actual offset! */ ASSERT(sizeof(struct trusty_startup_param) - + sizeof(struct key_info) < 0x1000, + + sizeof(struct key_info) < 0x1000U, "trusty_startup_param + key_info > 1Page size(4KB)!"); ASSERT(NR_WORLD == 2, "Only 2 Worlds supported!"); @@ -507,7 +507,7 @@ static void bsp_boot_post(void) pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name); - pr_dbg("Core %d is up", CPU_BOOT_ID); + pr_dbg("Core %hu is up", CPU_BOOT_ID); if (hardware_detect_support() != 0) { pr_fatal("hardware not support!\n"); @@ -606,7 +606,7 @@ static void cpu_secondary_post(void) /* Make sure rdtsc is enabled */ check_tsc(); - pr_dbg("Core %d is up", get_cpu_id()); + pr_dbg("Core %hu is up", get_cpu_id()); cpu_xsave_init(); @@ -616,7 +616,7 @@ static void cpu_secondary_post(void) timer_init(); /* Wait for boot processor to signal all secondary cores to continue */ - pcpu_sync_sleep(&pcpu_sync, 0); + pcpu_sync_sleep(&pcpu_sync, 0UL); ret = hv_main(get_cpu_id()); if (ret != 0) @@ -728,10 +728,10 @@ void start_cpus() timeout = CONFIG_CPU_UP_TIMEOUT * 1000; while ((up_count != expected_up) && (timeout != 0U)) { /* Delay 10us */ - udelay(10); + udelay(10U); /* Decrement timeout value */ - timeout -= 10; + timeout -= 10U; } /* Check to see if all expected CPUs are actually up */ @@ -761,10 +761,10 @@ void stop_cpus() expected_up = 1U; while ((up_count != expected_up) && (timeout != 0U)) { /* Delay 10us */ - udelay(10); + udelay(10U); /* Decrement timeout value */ - timeout -= 10; + timeout -= 10U; } if (up_count != expected_up) { @@ -864,7 +864,7 @@ static bool is_ctrl_setting_allowed(uint64_t msr_val, uint32_t ctrl) * - bitX in ctrl can be set 1 * only if bit 32+X in msr_val is 1 */ - return ((((uint32_t)(msr_val >> 32)) & ctrl) == ctrl); + return ((((uint32_t)(msr_val >> 32UL)) & ctrl) == ctrl); } static void vapic_cap_detect(void) @@ -908,17 +908,17 @@ static void vapic_cap_detect(void) bool is_vapic_supported(void) { - return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0); + return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0U); } bool is_vapic_intr_delivery_supported(void) { - return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0); + return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0U); } bool is_vapic_virt_reg_supported(void) { - return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0); + return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0U); } static void cpu_xsave_init(void) diff --git a/hypervisor/arch/x86/cpu_state_tbl.c b/hypervisor/arch/x86/cpu_state_tbl.c index 0cfe1c3a9..029ced7b1 100644 --- a/hypervisor/arch/x86/cpu_state_tbl.c +++ b/hypervisor/arch/x86/cpu_state_tbl.c @@ -8,67 +8,67 @@ /* The table includes cpu px info of Intel A3960 SoC */ static const struct cpu_px_data px_a3960[] = { - {0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */ - {0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */ - {0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */ - {0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */ - {0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */ - {0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */ - {0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */ - {0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */ - {0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */ - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */ - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */ - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */ - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */ - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */ - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */ - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */ - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */ + {0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */ + {0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */ + {0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */ + {0x834UL, 0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P3 */ + {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P4 */ + {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P5 */ + {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P6 */ + {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P7 */ + {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P8 */ + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P9 */ + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P10 */ + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P11 */ + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P12 */ + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P13 */ + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P14 */ + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P15 */ + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P16 */ }; /* The table includes cpu cx info of Intel A3960 SoC */ static const struct cpu_cx_data cx_a3960[] = { - {{SPACE_FFixedHW, 0x0, 0, 0, 0}, 0x1, 0x1, 0x3E8}, /* C1 */ - {{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */ - {{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */ + {{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */ + {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */ + {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */ }; /* The table includes cpu px info of Intel A3950 SoC */ static const struct cpu_px_data px_a3950[] = { - {0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */ - {0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */ - {0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */ - {0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */ - {0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */ - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */ - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */ - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */ - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */ - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */ - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */ - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */ - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */ + {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */ + {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */ + {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */ + {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P3 */ + {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P4 */ + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P5 */ + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P6 */ + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P7 */ + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */ + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */ + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */ + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P11 */ + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P12 */ }; /* The table includes cpu px info of Intel J3455 SoC */ static const struct cpu_px_data px_j3455[] = { - {0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */ - {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */ - {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */ - {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */ - {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */ - {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */ - {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */ - {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */ - {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P8 */ + {0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */ + {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */ + {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */ + {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P3 */ + {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P4 */ + {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P5 */ + {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P6 */ + {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P7 */ + {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P8 */ }; /* The table includes cpu cx info of Intel J3455 SoC */ static const struct cpu_cx_data cx_j3455[] = { - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x01}, 0x1, 0x1, 0x3E8}, /* C1 */ - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x21}, 0x2, 0x32, 0x0A}, /* C2 */ - {{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x60}, 0x3, 0x96, 0x0A} /* C3 */ + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x01UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */ + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x21UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */ + {{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x60UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */ }; static const struct cpu_state_table { @@ -113,7 +113,7 @@ void load_cpu_state_data(void) int tbl_idx; const struct cpu_state_info *state_info; - (void)memset(&boot_cpu_data.state_info, 0, + (void)memset(&boot_cpu_data.state_info, 0U, sizeof(struct cpu_state_info)); tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name); diff --git a/hypervisor/arch/x86/cpuid.c b/hypervisor/arch/x86/cpuid.c index 596a09ff3..cb187c61d 100644 --- a/hypervisor/arch/x86/cpuid.c +++ b/hypervisor/arch/x86/cpuid.c @@ -36,7 +36,7 @@ static inline struct vcpuid_entry *find_vcpuid_entry(struct vcpu *vcpu, if (entry == NULL) { uint32_t limit; - if ((leaf & 0x80000000) != 0U) + if ((leaf & 0x80000000U) != 0U) limit = vm->vcpuid_xlevel; else limit = vm->vcpuid_level; @@ -160,7 +160,7 @@ int set_vcpuid_entries(struct vm *vm) uint32_t limit; uint32_t i, j; - init_vcpuid_entry(vm, 0, 0, 0, &entry); + init_vcpuid_entry(vm, 0U, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; @@ -176,7 +176,7 @@ int set_vcpuid_entries(struct vm *vm) { uint32_t times; - init_vcpuid_entry(vm, i, 0, + init_vcpuid_entry(vm, i, 0U, CPUID_CHECK_SUBLEAF, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) @@ -212,7 +212,7 @@ int set_vcpuid_entries(struct vm *vm) break; default: - init_vcpuid_entry(vm, i, 0, 0, &entry); + init_vcpuid_entry(vm, i, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; @@ -220,24 +220,24 @@ int set_vcpuid_entries(struct vm *vm) } } - init_vcpuid_entry(vm, 0x40000000, 0, 0, &entry); + init_vcpuid_entry(vm, 0x40000000U, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; - init_vcpuid_entry(vm, 0x40000010, 0, 0, &entry); + init_vcpuid_entry(vm, 0x40000010U, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; - init_vcpuid_entry(vm, 0x80000000, 0, 0, &entry); + init_vcpuid_entry(vm, 0x80000000U, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; vm->vcpuid_xlevel = limit = entry.eax; for (i = 0x80000001U; i <= limit; i++) { - init_vcpuid_entry(vm, i, 0, 0, &entry); + init_vcpuid_entry(vm, i, 0U, 0U, &entry); result = set_vcpuid_entry(vm, &entry); if (result != 0) return result; @@ -309,7 +309,7 @@ void guest_cpuid(struct vcpu *vcpu, uint64_t cr4; /*read guest CR4*/ cr4 = exec_vmread(VMX_GUEST_CR4); - if ((cr4 & CR4_OSXSAVE) != 0U) + if ((cr4 & CR4_OSXSAVE) != 0UL) *ecx |= CPUID_ECX_OSXSAVE; } break; diff --git a/hypervisor/bsp/uefi/efi/boot.h b/hypervisor/bsp/uefi/efi/boot.h index 980a25150..85bd205a4 100644 --- a/hypervisor/bsp/uefi/efi/boot.h +++ b/hypervisor/bsp/uefi/efi/boot.h @@ -52,7 +52,7 @@ #define MSR_IA32_PAT 0x00000277 /* PAT */ #define MSR_IA32_EFER 0xC0000080 -#define MSR_IA32_FS_BASE 0xC0000100 +#define MSR_IA32_FS_BASE 0xC0000100U #define MSR_IA32_GS_BASE 0xC0000101 #define MSR_IA32_SYSENTER_ESP 0x00000175 /* ESP for sysenter */ #define MSR_IA32_SYSENTER_EIP 0x00000176 /* EIP for sysenter */ diff --git a/hypervisor/include/arch/x86/cpu.h b/hypervisor/include/arch/x86/cpu.h index 5c2a20f78..fe095c676 100644 --- a/hypervisor/include/arch/x86/cpu.h +++ b/hypervisor/include/arch/x86/cpu.h @@ -67,25 +67,25 @@ #define CR3_PCD (1U<<4) /* page-level cache disable */ /* CR4 register definitions */ -#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */ -#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */ -#define CR4_TSD (1U<<2) /* time stamp disable */ -#define CR4_DE (1U<<3) /* debugging extensions */ -#define CR4_PSE (1U<<4) /* page size extensions */ -#define CR4_PAE (1U<<5) /* physical address extensions */ -#define CR4_MCE (1U<<6) /* machine check enable */ -#define CR4_PGE (1U<<7) /* page global enable */ -#define CR4_PCE (1U<<8) +#define CR4_VME (1UL<<0) /* virtual 8086 mode extensions */ +#define CR4_PVI (1UL<<1) /* protected mode virtual interrupts */ +#define CR4_TSD (1UL<<2) /* time stamp disable */ +#define CR4_DE (1UL<<3) /* debugging extensions */ +#define CR4_PSE (1UL<<4) /* page size extensions */ +#define CR4_PAE (1UL<<5) /* physical address extensions */ +#define CR4_MCE (1UL<<6) /* machine check enable */ +#define CR4_PGE (1UL<<7) /* page global enable */ +#define CR4_PCE (1UL<<8) /* performance monitoring counter enable */ -#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */ -#define CR4_OSXMMEXCPT (1U<<10) +#define CR4_OSFXSR (1UL<<9) /* OS support for FXSAVE/FXRSTOR */ +#define CR4_OSXMMEXCPT (1UL<<10) /* OS support for unmasked SIMD floating point exceptions */ -#define CR4_VMXE (1U<<13) /* VMX enable */ -#define CR4_SMXE (1U<<14) /* SMX enable */ -#define CR4_PCIDE (1U<<17) /* PCID enable */ -#define CR4_OSXSAVE (1U<<18) -#define CR4_SMEP (1U<<20) -#define CR4_SMAP (1U<<21) +#define CR4_VMXE (1UL<<13) /* VMX enable */ +#define CR4_SMXE (1UL<<14) /* SMX enable */ +#define CR4_PCIDE (1UL<<17) /* PCID enable */ +#define CR4_OSXSAVE (1UL<<18) +#define CR4_SMEP (1UL<<20) +#define CR4_SMAP (1UL<<21) /* XSAVE and Processor Extended States enable bit */ @@ -197,18 +197,15 @@ extern spinlock_t trampoline_spinlock; ((uint64_t)_ld_cpu_data_end - (uint64_t)(_ld_cpu_data_start)) /* CPUID feature words */ -enum feature_word { - FEAT_1_ECX = 0, /* CPUID[1].ECX */ - FEAT_1_EDX, /* CPUID[1].EDX */ - FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ - FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ - FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ - FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ - FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ - FEAT_8000_0008_EBX, /* CPUID[8000_0008].EAX */ - FEATURE_WORDS, -}; - +#define FEAT_1_ECX 0U /* CPUID[1].ECX */ +#define FEAT_1_EDX 1U /* CPUID[1].EDX */ +#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */ +#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */ +#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */ +#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */ +#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */ +#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */ +#define FEATURE_WORDS 8U /** *The invalid cpu_id (INVALID_CPU_ID) is error *code for error handling, this means that diff --git a/hypervisor/include/arch/x86/cpufeatures.h b/hypervisor/include/arch/x86/cpufeatures.h index efb67e528..734ccd793 100644 --- a/hypervisor/include/arch/x86/cpufeatures.h +++ b/hypervisor/include/arch/x86/cpufeatures.h @@ -8,79 +8,79 @@ #define __X86_CPUFEATURES_H__ /* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/ -#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0) -#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1) -#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2) -#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3) -#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4) -#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5) -#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6) -#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7) -#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8) -#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9) -#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10) -#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12) -#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13) -#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14) -#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15) -#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17) -#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18) -#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19) -#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20) -#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21) -#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22) -#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23) -#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5) + 24) -#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25) -#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26) -#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27) -#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28) +#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5U) + 0U) +#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5U) + 1U) +#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5U) + 2U) +#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5U) + 3U) +#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5U) + 4U) +#define X86_FEATURE_VMX ((FEAT_1_ECX << 5U) + 5U) +#define X86_FEATURE_SMX ((FEAT_1_ECX << 5U) + 6U) +#define X86_FEATURE_EST ((FEAT_1_ECX << 5U) + 7U) +#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5U) + 8U) +#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5U) + 9U) +#define X86_FEATURE_CID ((FEAT_1_ECX << 5U) + 10U) +#define X86_FEATURE_FMA ((FEAT_1_ECX << 5U) + 12U) +#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5U) + 13U) +#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5U) + 14U) +#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5U) + 15U) +#define X86_FEATURE_PCID ((FEAT_1_ECX << 5U) + 17U) +#define X86_FEATURE_DCA ((FEAT_1_ECX << 5U) + 18U) +#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5U) + 19U) +#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5U) + 20U) +#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5U) + 21U) +#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5U) + 22U) +#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5U) + 23U) +#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5U) + 24U) +#define X86_FEATURE_AES ((FEAT_1_ECX << 5U) + 25U) +#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5U) + 26U) +#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5U) + 27U) +#define X86_FEATURE_AVX ((FEAT_1_ECX << 5U) + 28U) /* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/ -#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0) -#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1) -#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2) -#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3) -#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4) -#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5) -#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6) -#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7) -#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8) -#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9) -#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11) -#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12) -#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13) -#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14) -#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15) -#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16) -#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17) -#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18) -#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19) -#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21) -#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22) -#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23) -#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24) -#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25) -#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26) -#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27) -#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28) -#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29) -#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30) -#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31) +#define X86_FEATURE_FPU ((FEAT_1_EDX << 5U) + 0U) +#define X86_FEATURE_VME ((FEAT_1_EDX << 5U) + 1U) +#define X86_FEATURE_DE ((FEAT_1_EDX << 5U) + 2U) +#define X86_FEATURE_PSE ((FEAT_1_EDX << 5U) + 3U) +#define X86_FEATURE_TSC ((FEAT_1_EDX << 5U) + 4U) +#define X86_FEATURE_MSR ((FEAT_1_EDX << 5U) + 5U) +#define X86_FEATURE_PAE ((FEAT_1_EDX << 5U) + 6U) +#define X86_FEATURE_MCE ((FEAT_1_EDX << 5U) + 7U) +#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5U) + 8U) +#define X86_FEATURE_APIC ((FEAT_1_EDX << 5U) + 9U) +#define X86_FEATURE_SEP ((FEAT_1_EDX << 5U) + 11U) +#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5U) + 12U) +#define X86_FEATURE_PGE ((FEAT_1_EDX << 5U) + 13U) +#define X86_FEATURE_MCA ((FEAT_1_EDX << 5U) + 14U) +#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5U) + 15U) +#define X86_FEATURE_PAT ((FEAT_1_EDX << 5U) + 16U) +#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5U) + 17U) +#define X86_FEATURE_PSN ((FEAT_1_EDX << 5U) + 18U) +#define X86_FEATURE_CLF ((FEAT_1_EDX << 5U) + 19U) +#define X86_FEATURE_DTES ((FEAT_1_EDX << 5U) + 21U) +#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5U) + 22U) +#define X86_FEATURE_MMX ((FEAT_1_EDX << 5U) + 23U) +#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5U) + 24U) +#define X86_FEATURE_SSE ((FEAT_1_EDX << 5U) + 25U) +#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5U) + 26U) +#define X86_FEATURE_SS ((FEAT_1_EDX << 5U) + 27U) +#define X86_FEATURE_HTT ((FEAT_1_EDX << 5U) + 28U) +#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5U) + 29U) +#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5U) + 30U) +#define X86_FEATURE_PBE ((FEAT_1_EDX << 5U) + 31U) /* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/ -#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1) -#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5) + 7) -#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10) -#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5) + 20) +#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5U) + 1U) +#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5U) + 7U) +#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U) +#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U) /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/ -#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26) -#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27) +#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U) +#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U) /* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/ -#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5) + 20) -#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26) -#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5) + 29) +#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5U) + 20U) +#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U) +#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U) #endif /*__X86_CPUFEATURES_H__*/ diff --git a/hypervisor/include/arch/x86/cpuid.h b/hypervisor/include/arch/x86/cpuid.h index a27e51265..439ecd94f 100644 --- a/hypervisor/include/arch/x86/cpuid.h +++ b/hypervisor/include/arch/x86/cpuid.h @@ -89,12 +89,12 @@ #define CPUID_TLB 2 #define CPUID_SERIALNUM 3 #define CPUID_EXTEND_FEATURE 7 -#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000 -#define CPUID_EXTEND_FUNCTION_1 0x80000001 -#define CPUID_EXTEND_FUNCTION_2 0x80000002 -#define CPUID_EXTEND_FUNCTION_3 0x80000003 -#define CPUID_EXTEND_FUNCTION_4 0x80000004 -#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008 +#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U +#define CPUID_EXTEND_FUNCTION_1 0x80000001U +#define CPUID_EXTEND_FUNCTION_2 0x80000002U +#define CPUID_EXTEND_FUNCTION_3 0x80000003U +#define CPUID_EXTEND_FUNCTION_4 0x80000004U +#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U static inline void __cpuid(uint32_t *eax, uint32_t *ebx, @@ -112,7 +112,7 @@ static inline void cpuid(uint32_t leaf, uint32_t *ecx, uint32_t *edx) { *eax = leaf; - *ecx = 0; + *ecx = 0U; __cpuid(eax, ebx, ecx, edx); } diff --git a/hypervisor/include/arch/x86/guest/vcpu.h b/hypervisor/include/arch/x86/guest/vcpu.h index 8069be43d..a0b2bc576 100644 --- a/hypervisor/include/arch/x86/guest/vcpu.h +++ b/hypervisor/include/arch/x86/guest/vcpu.h @@ -48,29 +48,29 @@ #define CPU_CONTEXT_OFFSET_R15 104U #define CPU_CONTEXT_OFFSET_RDI 112U #define CPU_CONTEXT_OFFSET_CR0 120U -#define CPU_CONTEXT_OFFSET_RIP 152 -#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184 -#define CPU_CONTEXT_OFFSET_IA32_STAR 200 -#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208 -#define CPU_CONTEXT_OFFSET_IA32_FMASK 216 -#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224 -#define CPU_CONTEXT_OFFSET_CS 280 -#define CPU_CONTEXT_OFFSET_DS 344 -#define CPU_CONTEXT_OFFSET_ES 376 -#define CPU_CONTEXT_OFFSET_FS 408 -#define CPU_CONTEXT_OFFSET_GS 440 -#define CPU_CONTEXT_OFFSET_TR 472 -#define CPU_CONTEXT_OFFSET_GDTR 568 -#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608 #define CPU_CONTEXT_OFFSET_CR2 128U #define CPU_CONTEXT_OFFSET_CR3 136U #define CPU_CONTEXT_OFFSET_CR4 144U +#define CPU_CONTEXT_OFFSET_RIP 152U #define CPU_CONTEXT_OFFSET_RSP 160U #define CPU_CONTEXT_OFFSET_RFLAGS 168U +#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184U #define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192U +#define CPU_CONTEXT_OFFSET_IA32_STAR 200U +#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208U +#define CPU_CONTEXT_OFFSET_IA32_FMASK 216U +#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224U +#define CPU_CONTEXT_OFFSET_CS 280U #define CPU_CONTEXT_OFFSET_SS 312U +#define CPU_CONTEXT_OFFSET_DS 344U +#define CPU_CONTEXT_OFFSET_ES 376U +#define CPU_CONTEXT_OFFSET_FS 408U +#define CPU_CONTEXT_OFFSET_GS 440U +#define CPU_CONTEXT_OFFSET_TR 472U #define CPU_CONTEXT_OFFSET_IDTR 504U #define CPU_CONTEXT_OFFSET_LDTR 536U +#define CPU_CONTEXT_OFFSET_GDTR 568U +#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608U /*sizes of various registers within the VCPU data structure */ #define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE