From 47f883db301ef6a6af684cfd8c9939f70da92dd1 Mon Sep 17 00:00:00 2001 From: Sainath Grandhi Date: Thu, 19 Mar 2020 21:32:25 -0700 Subject: [PATCH] hv: Hypervisor access to PCI devices with 64-bit MMIO BARs PCI devices with 64-bit MMIO BARs and requiring large MMIO space can be assigned with physical address range at the very high end of platform supported physical address space. This patch uses the board info for 64-bit MMIO window as programmed by BIOS and constructs 1G page tables for the same. As ACRN uses identity mapping from Linear to Physical address space physical addresses upto 48 bit or 256TB can be supported. Tracked-On: #4586 Signed-off-by: Sainath Grandhi Acked-by: Eddie Dong --- hypervisor/arch/x86/mmu.c | 11 +++++++++++ hypervisor/arch/x86/page.c | 6 ++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/hypervisor/arch/x86/mmu.c b/hypervisor/arch/x86/mmu.c index c37c51568..6e12f56a3 100644 --- a/hypervisor/arch/x86/mmu.c +++ b/hypervisor/arch/x86/mmu.c @@ -38,6 +38,7 @@ #include #include #include +#include static void *ppt_mmu_pml4_addr; static uint8_t sanitized_page[PAGE_SIZE] __aligned(PAGE_SIZE); @@ -281,6 +282,16 @@ void init_paging(void) mmu_modify_or_del((uint64_t *)ppt_mmu_pml4_addr, (uint64_t)get_reserve_sworld_memory_base(), TRUSTY_RAM_SIZE * MAX_POST_VM_NUM, PAGE_USER, 0UL, &ppt_mem_ops, MR_MODIFY); #endif + + /* + * Users of this MMIO region needs to use access memory using stac/clac + */ + + if ((HI_MMIO_START != ~0UL) && (HI_MMIO_END != 0UL)) { + mmu_add((uint64_t *)ppt_mmu_pml4_addr, HI_MMIO_START, HI_MMIO_START, + (HI_MMIO_END - HI_MMIO_START), attr_uc, &ppt_mem_ops); + } + /* Enable paging */ enable_paging(); diff --git a/hypervisor/arch/x86/page.c b/hypervisor/arch/x86/page.c index 4f170656c..51a7e0ec2 100644 --- a/hypervisor/arch/x86/page.c +++ b/hypervisor/arch/x86/page.c @@ -13,8 +13,10 @@ #include #include -static struct page ppt_pml4_pages[PML4_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)]; -static struct page ppt_pdpt_pages[PDPT_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)]; +#define LINEAR_ADDRESS_SPACE_48_BIT (1UL << 48U) + +static struct page ppt_pml4_pages[PML4_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)]; +static struct page ppt_pdpt_pages[PDPT_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)]; static struct page ppt_pd_pages[PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)]; /* ppt: pripary page table */