From 48be6f1fd71e7042f8db9935cda3ea580847c9d6 Mon Sep 17 00:00:00 2001 From: Xiangyang Wu Date: Sat, 13 Apr 2019 16:24:32 +0800 Subject: [PATCH] HV:config:Add config to enable logic partition on KBL NUC i7 In the current design, logic partition scenario is supported on KBL NUC i7 since there is no related configuration and no the cooresponding boot loader supporting. The boot loader supporting is done in the previous patch. Add some configurations such physical PCI devices information, virtual e820 table etc for KBL NUC i7 to enable logical partition scenario. In the logical partition of KBL NUC i7, there are two pre-launched VM, this pre-launched VM doesn't support local APIC passthrough now. The hypervisor is booted through GRUB. TODO: In future, Local APIC passthrough and some real time fetures are needed for the logic partition scenario of KBL NUC i7. V5-->V6: Update "Tracked-On" Tracked-On: #2944 Signed-off-by: Xiangyang Wu Reviewed-by: Eddie Dong --- .../arch/x86/configs/nuc7i7bnh/pci_devices.h | 20 ++++++++++ hypervisor/arch/x86/configs/nuc7i7bnh/ve820.c | 37 ++++++++++++++++++- 2 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 hypervisor/arch/x86/configs/nuc7i7bnh/pci_devices.h diff --git a/hypervisor/arch/x86/configs/nuc7i7bnh/pci_devices.h b/hypervisor/arch/x86/configs/nuc7i7bnh/pci_devices.h new file mode 100644 index 000000000..de4c9b5a2 --- /dev/null +++ b/hypervisor/arch/x86/configs/nuc7i7bnh/pci_devices.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2019 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PCI_DEVICES_H_ +#define PCI_DEVICES_H_ + +#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U} +#define SATA_CONTROLLER .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U} +#define USB_CONTROLLER .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U} + +#define STORAGE_CONTROLLER_0 SATA_CONTROLLER +#define STORAGE_CONTROLLER_1 USB_CONTROLLER + +#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1fU, .f = 0x06U} +#define ETHERNET_CONTROLLER_1 + +#endif /* PCI_DEVICES_H_ */ diff --git a/hypervisor/arch/x86/configs/nuc7i7bnh/ve820.c b/hypervisor/arch/x86/configs/nuc7i7bnh/ve820.c index c1e5bedd3..d73d0447c 100644 --- a/hypervisor/arch/x86/configs/nuc7i7bnh/ve820.c +++ b/hypervisor/arch/x86/configs/nuc7i7bnh/ve820.c @@ -4,13 +4,46 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include +#define VE820_ENTRIES_KBL_NUC_i7 5U +static const struct e820_entry ve820_entry[VE820_ENTRIES_KBL_NUC_i7] = { + { /* usable RAM under 1MB */ + .baseaddr = 0x0UL, + .length = 0xF0000UL, /* 960KB */ + .type = E820_TYPE_RAM + }, + + { /* mptable */ + .baseaddr = 0xF0000UL, /* 960KB */ + .length = 0x10000UL, /* 16KB */ + .type = E820_TYPE_RESERVED + }, + + { /* lowmem */ + .baseaddr = 0x200000UL, /* 2MB */ + .length = 0x1FE00000UL, /* 510MB */ + .type = E820_TYPE_RAM + }, + + { /* between lowmem and PCI hole */ + .baseaddr = 0x20000000UL, /* 512MB */ + .length = 0xA0000000UL, /* 2560MB */ + .type = E820_TYPE_RESERVED + }, + + { /* between PCI hole and 4GB */ + .baseaddr = 0xe0000000UL, /* 3.5GB */ + .length = 0x20000000UL, /* 512MB */ + .type = E820_TYPE_RESERVED + }, +}; /** * @pre vm != NULL */ void create_prelaunched_vm_e820(struct acrn_vm *vm) { - vm->e820_entry_num = 0U; - vm->e820_entries = NULL; + vm->e820_entry_num = VE820_ENTRIES_KBL_NUC_i7; + vm->e820_entries = (struct e820_entry *)ve820_entry; }