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https://github.com/projectacrn/acrn-hypervisor.git
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hv: refine guest.c
- move `vcpumask2pcpumask` from `guest.c` to `vcpu.c` - move `prepare_sos_vm_memmap` from `guest.c` to `vm.c` - rename `guest.c` to `guest_memory.c` Tracked-On: #2484 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -176,7 +176,7 @@ C_SRCS += arch/x86/guest/vcpu.c
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C_SRCS += arch/x86/guest/vm.c
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C_SRCS += arch/x86/guest/vm.c
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C_SRCS += arch/x86/guest/vlapic.c
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C_SRCS += arch/x86/guest/vlapic.c
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C_SRCS += arch/x86/guest/vmtrr.c
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C_SRCS += arch/x86/guest/vmtrr.c
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C_SRCS += arch/x86/guest/guest.c
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C_SRCS += arch/x86/guest/guest_memory.c
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C_SRCS += arch/x86/guest/vmcall.c
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C_SRCS += arch/x86/guest/vmcall.c
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C_SRCS += arch/x86/guest/vmsr.c
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C_SRCS += arch/x86/guest/vmsr.c
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C_SRCS += arch/x86/guest/instr_emul.c
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C_SRCS += arch/x86/guest/instr_emul.c
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@ -27,22 +27,6 @@ struct page_walk_info {
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bool is_smep_on;
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bool is_smep_on;
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};
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};
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uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask)
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{
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uint16_t vcpu_id;
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uint64_t dmask = 0UL;
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struct acrn_vcpu *vcpu;
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for (vcpu_id = 0U; vcpu_id < vm->hw.created_vcpus; vcpu_id++) {
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if ((vdmask & (1UL << vcpu_id)) != 0UL) {
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vcpu = vcpu_from_vid(vm, vcpu_id);
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bitmap_set_nolock(vcpu->pcpu_id, &dmask);
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}
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}
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return dmask;
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}
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enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu)
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enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu)
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{
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{
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enum vm_cpu_mode cpu_mode;
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enum vm_cpu_mode cpu_mode;
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@ -440,57 +424,3 @@ int32_t copy_to_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
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{
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{
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return copy_gva(vcpu, h_ptr, gva, size, err_code, fault_addr, 0);
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return copy_gva(vcpu, h_ptr, gva, size, err_code, fault_addr, 0);
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}
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}
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/**
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* @param[inout] vm pointer to a vm descriptor
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*
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* @retval 0 on success
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*
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* @pre vm != NULL
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* @pre is_sos_vm(vm) == true
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*/
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void prepare_sos_vm_memmap(struct acrn_vm *vm)
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{
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uint32_t i;
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uint64_t attr_uc = (EPT_RWX | EPT_UNCACHED);
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uint64_t hv_hpa;
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uint64_t *pml4_page = (uint64_t *)vm->arch_vm.nworld_eptp;
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const struct e820_entry *entry;
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uint32_t entries_count = get_e820_entries_count();
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const struct e820_entry *p_e820 = get_e820_entry();
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const struct e820_mem_params *p_e820_mem_info = get_e820_mem_info();
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dev_dbg(ACRN_DBG_GUEST, "sos_vm: bottom memory - 0x%llx, top memory - 0x%llx\n",
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p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_top);
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if (p_e820_mem_info->mem_top > EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE)) {
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panic("Please configure SOS_VM_ADDRESS_SPACE correctly!\n");
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}
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/* create real ept map for all ranges with UC */
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ept_mr_add(vm, pml4_page, p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_bottom,
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(p_e820_mem_info->mem_top - p_e820_mem_info->mem_bottom), attr_uc);
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/* update ram entries to WB attr */
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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if (entry->type == E820_TYPE_RAM) {
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ept_mr_modify(vm, pml4_page, entry->baseaddr, entry->length, EPT_WB, EPT_MT_MASK);
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}
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}
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dev_dbg(ACRN_DBG_GUEST, "SOS_VM e820 layout:\n");
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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dev_dbg(ACRN_DBG_GUEST, "e820 table: %d type: 0x%x", i, entry->type);
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dev_dbg(ACRN_DBG_GUEST, "BaseAddress: 0x%016llx length: 0x%016llx\n",
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entry->baseaddr, entry->length);
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}
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/* unmap hypervisor itself for safety
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* will cause EPT violation if sos accesses hv memory
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*/
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hv_hpa = get_hv_image_base();
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ept_mr_del(vm, pml4_page, hv_hpa, CONFIG_HV_RAM_SIZE);
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}
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@ -676,3 +676,19 @@ int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id)
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return ret;
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return ret;
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}
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}
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uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask)
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{
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uint16_t vcpu_id;
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uint64_t dmask = 0UL;
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struct acrn_vcpu *vcpu;
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for (vcpu_id = 0U; vcpu_id < vm->hw.created_vcpus; vcpu_id++) {
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if ((vdmask & (1UL << vcpu_id)) != 0UL) {
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vcpu = vcpu_from_vid(vm, vcpu_id);
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bitmap_set_nolock(vcpu->pcpu_id, &dmask);
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}
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}
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return dmask;
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}
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@ -9,6 +9,7 @@
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#include <multiboot.h>
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#include <multiboot.h>
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#include <e820.h>
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#include <e820.h>
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#include <vtd.h>
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#include <vtd.h>
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#include <reloc.h>
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vm_sw_loader_t vm_sw_loader;
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vm_sw_loader_t vm_sw_loader;
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@ -110,6 +111,59 @@ uint16_t get_vm_pcpu_nums(struct acrn_vm_config *vm_config)
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}
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}
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#endif
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#endif
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/**
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* @param[inout] vm pointer to a vm descriptor
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*
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* @retval 0 on success
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*
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* @pre vm != NULL
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* @pre is_sos_vm(vm) == true
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*/
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static void prepare_sos_vm_memmap(struct acrn_vm *vm)
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{
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uint32_t i;
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uint64_t attr_uc = (EPT_RWX | EPT_UNCACHED);
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uint64_t hv_hpa;
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uint64_t *pml4_page = (uint64_t *)vm->arch_vm.nworld_eptp;
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const struct e820_entry *entry;
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uint32_t entries_count = get_e820_entries_count();
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const struct e820_entry *p_e820 = get_e820_entry();
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const struct e820_mem_params *p_e820_mem_info = get_e820_mem_info();
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pr_dbg("sos_vm: bottom memory - 0x%llx, top memory - 0x%llx\n",
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p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_top);
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if (p_e820_mem_info->mem_top > EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE)) {
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panic("Please configure SOS_VM_ADDRESS_SPACE correctly!\n");
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}
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/* create real ept map for all ranges with UC */
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ept_mr_add(vm, pml4_page, p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_bottom,
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(p_e820_mem_info->mem_top - p_e820_mem_info->mem_bottom), attr_uc);
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/* update ram entries to WB attr */
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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if (entry->type == E820_TYPE_RAM) {
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ept_mr_modify(vm, pml4_page, entry->baseaddr, entry->length, EPT_WB, EPT_MT_MASK);
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}
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}
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pr_dbg("SOS_VM e820 layout:\n");
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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pr_dbg("e820 table: %d type: 0x%x", i, entry->type);
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pr_dbg("BaseAddress: 0x%016llx length: 0x%016llx\n", entry->baseaddr, entry->length);
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}
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/* unmap hypervisor itself for safety
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* will cause EPT violation if sos accesses hv memory
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*/
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hv_hpa = get_hv_image_base();
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ept_mr_del(vm, pml4_page, hv_hpa, CONFIG_HV_RAM_SIZE);
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}
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/**
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/**
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* @pre vm_id < CONFIG_MAX_VM_NUM && vm_config != NULL && rtn_vm != NULL
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* @pre vm_id < CONFIG_MAX_VM_NUM && vm_config != NULL && rtn_vm != NULL
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*/
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*/
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@ -70,8 +70,6 @@
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#define LDTR_AR (0x0082U) /* LDT, type must be 2, refer to SDM Vol3 26.3.1.2 */
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#define LDTR_AR (0x0082U) /* LDT, type must be 2, refer to SDM Vol3 26.3.1.2 */
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#define TR_AR (0x008bU) /* TSS (busy), refer to SDM Vol3 26.3.1.2 */
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#define TR_AR (0x008bU) /* TSS (busy), refer to SDM Vol3 26.3.1.2 */
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void prepare_sos_vm_memmap(struct acrn_vm *vm);
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/* Use # of paging level to identify paging mode */
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/* Use # of paging level to identify paging mode */
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enum vm_paging_mode {
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enum vm_paging_mode {
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PAGING_MODE_0_LEVEL = 0U, /* Flat */
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PAGING_MODE_0_LEVEL = 0U, /* Flat */
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@ -84,8 +82,6 @@ enum vm_paging_mode {
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/*
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/*
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* VM related APIs
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* VM related APIs
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*/
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*/
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uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask);
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int32_t gva2gpa(struct acrn_vcpu *vcpu, uint64_t gva, uint64_t *gpa, uint32_t *err_code);
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int32_t gva2gpa(struct acrn_vcpu *vcpu, uint64_t gva, uint64_t *gpa, uint32_t *err_code);
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enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu);
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enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu);
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@ -599,6 +599,16 @@ void schedule_vcpu(struct acrn_vcpu *vcpu);
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*/
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*/
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int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id);
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int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id);
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/**
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* @brief get physical destination cpu mask
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*
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* get the corresponding physical destination cpu mask for the vm and virtual destination cpu mask
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*
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* @param[in] vm pointer to vm data structure
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* @param[in] vdmask virtual destination cpu mask
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*/
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uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask);
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/**
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/**
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* @}
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* @}
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*/
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*/
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