hv: refine guest.c

- move `vcpumask2pcpumask` from `guest.c` to `vcpu.c`
- move `prepare_sos_vm_memmap` from `guest.c` to `vm.c`
- rename `guest.c` to `guest_memory.c`

Tracked-On: #2484
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao 2019-02-01 13:56:17 +08:00 committed by Eddie Dong
parent be946ca8e0
commit 49623fc073
6 changed files with 81 additions and 75 deletions

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@ -176,7 +176,7 @@ C_SRCS += arch/x86/guest/vcpu.c
C_SRCS += arch/x86/guest/vm.c C_SRCS += arch/x86/guest/vm.c
C_SRCS += arch/x86/guest/vlapic.c C_SRCS += arch/x86/guest/vlapic.c
C_SRCS += arch/x86/guest/vmtrr.c C_SRCS += arch/x86/guest/vmtrr.c
C_SRCS += arch/x86/guest/guest.c C_SRCS += arch/x86/guest/guest_memory.c
C_SRCS += arch/x86/guest/vmcall.c C_SRCS += arch/x86/guest/vmcall.c
C_SRCS += arch/x86/guest/vmsr.c C_SRCS += arch/x86/guest/vmsr.c
C_SRCS += arch/x86/guest/instr_emul.c C_SRCS += arch/x86/guest/instr_emul.c

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@ -27,22 +27,6 @@ struct page_walk_info {
bool is_smep_on; bool is_smep_on;
}; };
uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask)
{
uint16_t vcpu_id;
uint64_t dmask = 0UL;
struct acrn_vcpu *vcpu;
for (vcpu_id = 0U; vcpu_id < vm->hw.created_vcpus; vcpu_id++) {
if ((vdmask & (1UL << vcpu_id)) != 0UL) {
vcpu = vcpu_from_vid(vm, vcpu_id);
bitmap_set_nolock(vcpu->pcpu_id, &dmask);
}
}
return dmask;
}
enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu) enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu)
{ {
enum vm_cpu_mode cpu_mode; enum vm_cpu_mode cpu_mode;
@ -440,57 +424,3 @@ int32_t copy_to_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
{ {
return copy_gva(vcpu, h_ptr, gva, size, err_code, fault_addr, 0); return copy_gva(vcpu, h_ptr, gva, size, err_code, fault_addr, 0);
} }
/**
* @param[inout] vm pointer to a vm descriptor
*
* @retval 0 on success
*
* @pre vm != NULL
* @pre is_sos_vm(vm) == true
*/
void prepare_sos_vm_memmap(struct acrn_vm *vm)
{
uint32_t i;
uint64_t attr_uc = (EPT_RWX | EPT_UNCACHED);
uint64_t hv_hpa;
uint64_t *pml4_page = (uint64_t *)vm->arch_vm.nworld_eptp;
const struct e820_entry *entry;
uint32_t entries_count = get_e820_entries_count();
const struct e820_entry *p_e820 = get_e820_entry();
const struct e820_mem_params *p_e820_mem_info = get_e820_mem_info();
dev_dbg(ACRN_DBG_GUEST, "sos_vm: bottom memory - 0x%llx, top memory - 0x%llx\n",
p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_top);
if (p_e820_mem_info->mem_top > EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE)) {
panic("Please configure SOS_VM_ADDRESS_SPACE correctly!\n");
}
/* create real ept map for all ranges with UC */
ept_mr_add(vm, pml4_page, p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_bottom,
(p_e820_mem_info->mem_top - p_e820_mem_info->mem_bottom), attr_uc);
/* update ram entries to WB attr */
for (i = 0U; i < entries_count; i++) {
entry = p_e820 + i;
if (entry->type == E820_TYPE_RAM) {
ept_mr_modify(vm, pml4_page, entry->baseaddr, entry->length, EPT_WB, EPT_MT_MASK);
}
}
dev_dbg(ACRN_DBG_GUEST, "SOS_VM e820 layout:\n");
for (i = 0U; i < entries_count; i++) {
entry = p_e820 + i;
dev_dbg(ACRN_DBG_GUEST, "e820 table: %d type: 0x%x", i, entry->type);
dev_dbg(ACRN_DBG_GUEST, "BaseAddress: 0x%016llx length: 0x%016llx\n",
entry->baseaddr, entry->length);
}
/* unmap hypervisor itself for safety
* will cause EPT violation if sos accesses hv memory
*/
hv_hpa = get_hv_image_base();
ept_mr_del(vm, pml4_page, hv_hpa, CONFIG_HV_RAM_SIZE);
}

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@ -676,3 +676,19 @@ int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id)
return ret; return ret;
} }
uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask)
{
uint16_t vcpu_id;
uint64_t dmask = 0UL;
struct acrn_vcpu *vcpu;
for (vcpu_id = 0U; vcpu_id < vm->hw.created_vcpus; vcpu_id++) {
if ((vdmask & (1UL << vcpu_id)) != 0UL) {
vcpu = vcpu_from_vid(vm, vcpu_id);
bitmap_set_nolock(vcpu->pcpu_id, &dmask);
}
}
return dmask;
}

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@ -9,6 +9,7 @@
#include <multiboot.h> #include <multiboot.h>
#include <e820.h> #include <e820.h>
#include <vtd.h> #include <vtd.h>
#include <reloc.h>
vm_sw_loader_t vm_sw_loader; vm_sw_loader_t vm_sw_loader;
@ -110,6 +111,59 @@ uint16_t get_vm_pcpu_nums(struct acrn_vm_config *vm_config)
} }
#endif #endif
/**
* @param[inout] vm pointer to a vm descriptor
*
* @retval 0 on success
*
* @pre vm != NULL
* @pre is_sos_vm(vm) == true
*/
static void prepare_sos_vm_memmap(struct acrn_vm *vm)
{
uint32_t i;
uint64_t attr_uc = (EPT_RWX | EPT_UNCACHED);
uint64_t hv_hpa;
uint64_t *pml4_page = (uint64_t *)vm->arch_vm.nworld_eptp;
const struct e820_entry *entry;
uint32_t entries_count = get_e820_entries_count();
const struct e820_entry *p_e820 = get_e820_entry();
const struct e820_mem_params *p_e820_mem_info = get_e820_mem_info();
pr_dbg("sos_vm: bottom memory - 0x%llx, top memory - 0x%llx\n",
p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_top);
if (p_e820_mem_info->mem_top > EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE)) {
panic("Please configure SOS_VM_ADDRESS_SPACE correctly!\n");
}
/* create real ept map for all ranges with UC */
ept_mr_add(vm, pml4_page, p_e820_mem_info->mem_bottom, p_e820_mem_info->mem_bottom,
(p_e820_mem_info->mem_top - p_e820_mem_info->mem_bottom), attr_uc);
/* update ram entries to WB attr */
for (i = 0U; i < entries_count; i++) {
entry = p_e820 + i;
if (entry->type == E820_TYPE_RAM) {
ept_mr_modify(vm, pml4_page, entry->baseaddr, entry->length, EPT_WB, EPT_MT_MASK);
}
}
pr_dbg("SOS_VM e820 layout:\n");
for (i = 0U; i < entries_count; i++) {
entry = p_e820 + i;
pr_dbg("e820 table: %d type: 0x%x", i, entry->type);
pr_dbg("BaseAddress: 0x%016llx length: 0x%016llx\n", entry->baseaddr, entry->length);
}
/* unmap hypervisor itself for safety
* will cause EPT violation if sos accesses hv memory
*/
hv_hpa = get_hv_image_base();
ept_mr_del(vm, pml4_page, hv_hpa, CONFIG_HV_RAM_SIZE);
}
/** /**
* @pre vm_id < CONFIG_MAX_VM_NUM && vm_config != NULL && rtn_vm != NULL * @pre vm_id < CONFIG_MAX_VM_NUM && vm_config != NULL && rtn_vm != NULL
*/ */

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@ -70,8 +70,6 @@
#define LDTR_AR (0x0082U) /* LDT, type must be 2, refer to SDM Vol3 26.3.1.2 */ #define LDTR_AR (0x0082U) /* LDT, type must be 2, refer to SDM Vol3 26.3.1.2 */
#define TR_AR (0x008bU) /* TSS (busy), refer to SDM Vol3 26.3.1.2 */ #define TR_AR (0x008bU) /* TSS (busy), refer to SDM Vol3 26.3.1.2 */
void prepare_sos_vm_memmap(struct acrn_vm *vm);
/* Use # of paging level to identify paging mode */ /* Use # of paging level to identify paging mode */
enum vm_paging_mode { enum vm_paging_mode {
PAGING_MODE_0_LEVEL = 0U, /* Flat */ PAGING_MODE_0_LEVEL = 0U, /* Flat */
@ -84,8 +82,6 @@ enum vm_paging_mode {
/* /*
* VM related APIs * VM related APIs
*/ */
uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask);
int32_t gva2gpa(struct acrn_vcpu *vcpu, uint64_t gva, uint64_t *gpa, uint32_t *err_code); int32_t gva2gpa(struct acrn_vcpu *vcpu, uint64_t gva, uint64_t *gpa, uint32_t *err_code);
enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu); enum vm_paging_mode get_vcpu_paging_mode(struct acrn_vcpu *vcpu);

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@ -599,6 +599,16 @@ void schedule_vcpu(struct acrn_vcpu *vcpu);
*/ */
int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id); int32_t prepare_vcpu(struct acrn_vm *vm, uint16_t pcpu_id);
/**
* @brief get physical destination cpu mask
*
* get the corresponding physical destination cpu mask for the vm and virtual destination cpu mask
*
* @param[in] vm pointer to vm data structure
* @param[in] vdmask virtual destination cpu mask
*/
uint64_t vcpumask2pcpumask(struct acrn_vm *vm, uint64_t vdmask);
/** /**
* @} * @}
*/ */