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HV: debug: support 64bit BAR pci uart with 32bit space

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Currently the HV console does not support PCI UART with 64bit BAR, but in the
case that the BAR is in 64bit and the BAR space is below 4GB (i.e. the high
32bit address of the 64bit BAR is zero), HV should be able to support it.

Tracked-On: #6334

Signed-off-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Victor Sun 2021-07-30 10:23:50 +08:00 committed by wenlingz
parent 2fbc4c26e6
commit 4a53a23faa
1 changed files with 5 additions and 1 deletions
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6
hypervisor/debug/uart16550.c
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@ -155,11 +155,15 @@ void uart16550_init(bool early_boot)
uart.reg_width = 1; uart.reg_width = 1;
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN); pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
} else { } else {
if ((bar0 & 0xfU) == 0U) { /* 32 bits MMIO Space */ uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
/* Enable the PCI UART if the BAR is 32bit, or 64bit with 4GB- mmio space. */
if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U) == 4U) && (bar_hi == 0U))) {
uart.type = MMIO; uart.type = MMIO;
uart.mmio_base_vaddr = hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK)); uart.mmio_base_vaddr = hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN); pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
} else { } else {
/* TODO: enable 64bit BAR with 4GB+ mmio space */
uart.enabled = false; uart.enabled = false;
return; return;
} }