From 4a683ed10ead1c4aecddb62a8e414665877de484 Mon Sep 17 00:00:00 2001 From: "Li, Fei1" Date: Fri, 15 Mar 2019 00:04:18 +0800 Subject: [PATCH] hv: vlapic: minor fix for update_msr_bitmap_x2apic_apicv Shouldn't trap TPR since we always enable "Use TPR shadow" Tracked-On: #1842 Signed-off-by: Li, Fei1 --- hypervisor/arch/x86/guest/vmsr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c index b38900c1f..60a562283 100644 --- a/hypervisor/arch/x86/guest/vmsr.c +++ b/hypervisor/arch/x86/guest/vmsr.c @@ -640,10 +640,11 @@ void update_msr_bitmap_x2apic_apicv(const struct acrn_vcpu *vcpu) * writes to them are virtualized with Register Virtualization * Refer to Section 29.1 in Intel SDM Vol. 3 */ - enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE); enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_EOI, INTERCEPT_READ); enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_SELF_IPI, INTERCEPT_READ); } + + enable_msr_interception(msr_bitmap, MSR_IA32_EXT_APIC_TPR, INTERCEPT_DISABLE); } /*