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hv: pci: rename CFG read/write function for PCI-compatible Configuration Mechanism

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Move CFG read/write function for PCI-compatible Configuration Mechanism from
debug/uartuart16550.c to hw/pci.c and rename CFG read/write function for
PCI-compatible Configuration Mechanism to pci_pio_read/write_cfg to align with
CFG read/write function pci_mmcfg_read/write_cfg for PCI Express Enhanced
Configuration Access Mechanism.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1 2020-03-11 13:52:16 +08:00 committed by wenlingz
parent 7e74ed557b
commit 4b6dd19ad1
4 changed files with 82 additions and 83 deletions
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61
hypervisor/debug/uart16550.c
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@ -46,67 +46,6 @@ typedef uint32_t uart_reg_t;
static union pci_bdf serial_pci_bdf;
static uint32_t pci_direct_calc_address(union pci_bdf bdf, uint32_t offset)
{
uint32_t addr = (uint32_t)bdf.value;
addr <<= 8U;
addr |= (offset | PCI_CFG_ENABLE);
return addr;
}
static uint32_t pci_direct_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
{
uint32_t addr;
uint32_t val;
addr = pci_direct_calc_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Read result from DATA register */
switch (bytes) {
case 1U:
val = (uint32_t)pio_read8((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
val = (uint32_t)pio_read16((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
val = pio_read32((uint16_t)PCI_CONFIG_DATA);
break;
}
return val;
}
static void pci_direct_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
{
uint32_t addr = pci_direct_calc_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Write value to DATA register */
switch (bytes) {
case 1U:
pio_write8((uint8_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
pio_write16((uint16_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
pio_write32(val, (uint16_t)PCI_CONFIG_DATA);
break;
}
}
struct pci_cfg_ops pci_direct_cfg_ops = {
.pci_read_cfg = pci_direct_read_cfg,
.pci_write_cfg = pci_direct_write_cfg,
};
/* PCI BDF must follow format: bus:dev.func, for example 0:18.2 */
static uint16_t get_pci_bdf_value(char *bdf)
{

99
hypervisor/hw/pci.c
View File

@ -61,17 +61,92 @@ uint64_t get_mmcfg_base(void)
return pci_mmcfg_base;
}
#if defined(HV_DEBUG)
static inline uint32_t pio_off_to_address(union pci_bdf bdf, uint32_t offset)
{
uint32_t addr = (uint32_t)bdf.value;
addr <<= 8U;
addr |= (offset | PCI_CFG_ENABLE);
return addr;
}
static uint32_t pci_pio_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
{
uint32_t addr;
uint32_t val;
addr = pio_off_to_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Read result from DATA register */
switch (bytes) {
case 1U:
val = (uint32_t)pio_read8((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
val = (uint32_t)pio_read16((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
val = pio_read32((uint16_t)PCI_CONFIG_DATA);
break;
}
return val;
}
static void pci_pio_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
{
uint32_t addr = pio_off_to_address(bdf, offset);
/* Write address to ADDRESS register */
pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
/* Write value to DATA register */
switch (bytes) {
case 1U:
pio_write8((uint8_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break;
case 2U:
pio_write16((uint16_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break;
default:
pio_write32(val, (uint16_t)PCI_CONFIG_DATA);
break;
}
}
#else
static uint32_t pci_pio_read_cfg(__unused union pci_bdf bdf,
__unused uint32_t offset, __unused uint32_t bytes)
{
return ~0U;
}
static void pci_pio_write_cfg(__unused union pci_bdf bdf,
__unused uint32_t offset, __unused uint32_t bytes, __unused uint32_t val)
{
}
#endif
static const struct pci_cfg_ops pci_pio_cfg_ops = {
.pci_read_cfg = pci_pio_read_cfg,
.pci_write_cfg = pci_pio_write_cfg,
};
/*
* @pre offset < 0x1000U
*/
static inline uint32_t pci_mmcfg_calc_address(union pci_bdf bdf, uint32_t offset)
static inline uint32_t mmcfg_off_to_address(union pci_bdf bdf, uint32_t offset)
{
return (uint32_t)pci_mmcfg_base + (((uint32_t)bdf.value << 12U) | offset);
}
static uint32_t pci_mmcfg_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
{
uint32_t addr = pci_mmcfg_calc_address(bdf, offset);
uint32_t addr = mmcfg_off_to_address(bdf, offset);
void *hva = hpa2hva(addr);
uint32_t val;
@ -97,7 +172,7 @@ static uint32_t pci_mmcfg_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t
*/
static void pci_mmcfg_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
{
uint32_t addr = pci_mmcfg_calc_address(bdf, offset);
uint32_t addr = mmcfg_off_to_address(bdf, offset);
void *hva = hpa2hva(addr);
spinlock_obtain(&pci_device_lock);
@ -115,12 +190,12 @@ static void pci_mmcfg_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t byt
spinlock_release(&pci_device_lock);
}
static struct pci_cfg_ops pci_mmcfg_cfg_ops = {
static const struct pci_cfg_ops pci_mmcfg_cfg_ops = {
.pci_read_cfg = pci_mmcfg_read_cfg,
.pci_write_cfg = pci_mmcfg_write_cfg,
};
static struct pci_cfg_ops *acrn_pci_cfg_ops = &pci_direct_cfg_ops;
static const struct pci_cfg_ops *acrn_pci_cfg_ops = &pci_pio_cfg_ops;
void pci_switch_to_mmio_cfg_ops(void)
{
@ -135,12 +210,7 @@ uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
{
uint32_t val = ~0U;
/* The pci_read_cfg would not be empty unless be called before
* pci_switch_to_mmio_cfg_ops in release version.
*/
if (acrn_pci_cfg_ops->pci_read_cfg != NULL) {
val = acrn_pci_cfg_ops->pci_read_cfg(bdf, offset, bytes);
}
val = acrn_pci_cfg_ops->pci_read_cfg(bdf, offset, bytes);
return val;
}
@ -151,12 +221,7 @@ uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
*/
void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
{
/* The pci_write_cfg would not be empty unless be called before
* pci_switch_to_mmio_cfg_ops in release version.
*/
if (acrn_pci_cfg_ops->pci_write_cfg != NULL) {
acrn_pci_cfg_ops->pci_write_cfg(bdf, offset, bytes, val);
}
acrn_pci_cfg_ops->pci_write_cfg(bdf, offset, bytes, val);
}
bool pdev_need_bar_restore(const struct pci_pdev *pdev)

4
hypervisor/include/debug/uart16550.h
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@ -7,8 +7,6 @@
#ifndef UART16550_H
#define UART16550_H
#include <pci.h>
/* Register / bit definitions for 16c550 uart */
/*receive buffer register | base+00h, dlab=0b r*/
#define UART16550_RBR 0x00U
@ -129,8 +127,6 @@
/* UART oscillator clock */
#define UART_CLOCK_RATE 1843200U /* 1.8432 MHz */
extern struct pci_cfg_ops pci_direct_cfg_ops;
void uart16550_init(bool early_boot);
char uart16550_getc(void);
size_t uart16550_puts(const char *buf, uint32_t len);

1
hypervisor/release/uart16550.c
View File

@ -8,4 +8,3 @@
#include <pci.h>
void uart16550_init(__unused bool early_boot) {}
struct pci_cfg_ops pci_direct_cfg_ops;