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hv: refined the pmu passthru irq handling

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This patch refined the pmu passthru irq handling, which will re-enable
the PMC interrupt in the vlapic handler. So that can avoid some
interrupt storm situation happens.

This patch can fix the remaining Android perf CTS failure.

Tracked-On: #2598
Signed-off-by: Min He <min.he@intel.com>
This commit is contained in:
Min He 2019-03-06 05:54:05 +00:00 committed by wenlingz
parent 9d4b18dc2e
commit 4fa293c402
2 changed files with 7 additions and 1 deletions
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7
hypervisor/arch/x86/guest/vlapic.c
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@ -714,6 +714,13 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
*lvtptr = val;
idx = lvt_off_to_idx(offset);
atomic_store32(&vlapic->lvt_last[idx], val);
#if defined(HV_DEBUG) && !defined(PROFILING_ON)
if ((offset == APIC_OFFSET_PERF_LVT) &&
(val == APIC_LVT_DM_NMI)) {
msr_write(MSR_IA32_EXT_APIC_LVT_PMI, VECTOR_PMI);
}
#endif
}
static void

1
hypervisor/debug/profiling.c
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@ -1460,7 +1460,6 @@ static void pmu_passthru_pmi_handler(__unused uint32_t irq, __unused void *data)
msr_write(MSR_IA32_EXT_APIC_LVT_PMI, VECTOR_PMI|LAPIC_LVT_MASK);
vlapic_set_local_intr(vcpu->vm, vcpu->vcpu_id, APIC_LVT_PMC);
msr_write(MSR_IA32_EXT_APIC_LVT_PMI, VECTOR_PMI);
}
void profiling_setup(void)