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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-19 20:22:46 +00:00
hv: vmexit: fix MISRA-C violations related to multiple exits
This patch fixes the MISRA-C violations in arch/x86/vmexit.c * make the function have only one exit point Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
wenlingz
parent
0a713e6fbc
commit
50f5b0f6bb
@ -160,69 +160,61 @@ int32_t vmexit_handler(struct acrn_vcpu *vcpu)
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if (get_cpu_id() != vcpu->pcpu_id) {
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if (get_cpu_id() != vcpu->pcpu_id) {
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pr_fatal("vcpu is not running on its pcpu!");
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pr_fatal("vcpu is not running on its pcpu!");
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return -EINVAL;
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ret = -EINVAL;
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}
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/* Obtain interrupt info */
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vcpu->arch.idt_vectoring_info =
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exec_vmread32(VMX_IDT_VEC_INFO_FIELD);
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/* Filter out HW exception & NMI */
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if ((vcpu->arch.idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
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uint32_t vector_info = vcpu->arch.idt_vectoring_info;
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uint32_t vector = vector_info & 0xffU;
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uint32_t type = (vector_info & VMX_INT_TYPE_MASK) >> 8U;
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uint32_t err_code = 0U;
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if (type == VMX_INT_TYPE_HW_EXP) {
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if ((vector_info & VMX_INT_INFO_ERR_CODE_VALID) != 0U) {
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err_code = exec_vmread32(VMX_IDT_VEC_ERROR_CODE);
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}
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(void)vcpu_queue_exception(vcpu, vector, err_code);
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vcpu->arch.idt_vectoring_info = 0U;
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} else if (type == VMX_INT_TYPE_NMI) {
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vcpu_make_request(vcpu, ACRN_REQUEST_NMI);
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vcpu->arch.idt_vectoring_info = 0U;
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} else {
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/* No action on EXT_INT or SW exception. */
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}
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}
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/* Calculate basic exit reason (low 16-bits) */
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basic_exit_reason = (uint16_t)(vcpu->arch.exit_reason & 0xFFFFU);
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/* Log details for exit */
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pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
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/* Ensure exit reason is within dispatch table */
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if (basic_exit_reason >= ARRAY_SIZE(dispatch_table)) {
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pr_err("Invalid Exit Reason: 0x%016llx ",
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vcpu->arch.exit_reason);
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return -EINVAL;
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}
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/* Calculate dispatch table entry */
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dispatch = (struct vm_exit_dispatch *)
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(dispatch_table + basic_exit_reason);
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/* See if an exit qualification is necessary for this exit
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* handler
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*/
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if (dispatch->need_exit_qualification != 0U) {
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/* Get exit qualification */
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vcpu->arch.exit_qualification =
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exec_vmread(VMX_EXIT_QUALIFICATION);
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}
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/* exit dispatch handling */
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if (basic_exit_reason == VMX_EXIT_REASON_EXTERNAL_INTERRUPT) {
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/* Handling external_interrupt
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* should disable intr
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*/
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CPU_IRQ_DISABLE();
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ret = dispatch->handler(vcpu);
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CPU_IRQ_ENABLE();
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} else {
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} else {
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ret = dispatch->handler(vcpu);
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/* Obtain interrupt info */
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vcpu->arch.idt_vectoring_info = exec_vmread32(VMX_IDT_VEC_INFO_FIELD);
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/* Filter out HW exception & NMI */
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if ((vcpu->arch.idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
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uint32_t vector_info = vcpu->arch.idt_vectoring_info;
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uint32_t vector = vector_info & 0xffU;
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uint32_t type = (vector_info & VMX_INT_TYPE_MASK) >> 8U;
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uint32_t err_code = 0U;
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if (type == VMX_INT_TYPE_HW_EXP) {
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if ((vector_info & VMX_INT_INFO_ERR_CODE_VALID) != 0U) {
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err_code = exec_vmread32(VMX_IDT_VEC_ERROR_CODE);
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}
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(void)vcpu_queue_exception(vcpu, vector, err_code);
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vcpu->arch.idt_vectoring_info = 0U;
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} else if (type == VMX_INT_TYPE_NMI) {
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vcpu_make_request(vcpu, ACRN_REQUEST_NMI);
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vcpu->arch.idt_vectoring_info = 0U;
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} else {
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/* No action on EXT_INT or SW exception. */
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}
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}
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/* Calculate basic exit reason (low 16-bits) */
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basic_exit_reason = (uint16_t)(vcpu->arch.exit_reason & 0xFFFFU);
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/* Log details for exit */
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pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
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/* Ensure exit reason is within dispatch table */
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if (basic_exit_reason >= ARRAY_SIZE(dispatch_table)) {
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pr_err("Invalid Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
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ret = -EINVAL;
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} else {
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/* Calculate dispatch table entry */
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dispatch = (struct vm_exit_dispatch *)(dispatch_table + basic_exit_reason);
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/* See if an exit qualification is necessary for this exit handler */
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if (dispatch->need_exit_qualification != 0U) {
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/* Get exit qualification */
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vcpu->arch.exit_qualification = exec_vmread(VMX_EXIT_QUALIFICATION);
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}
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/* exit dispatch handling */
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if (basic_exit_reason == VMX_EXIT_REASON_EXTERNAL_INTERRUPT) {
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/* Handling external_interrupt should disable intr */
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CPU_IRQ_DISABLE();
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ret = dispatch->handler(vcpu);
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CPU_IRQ_ENABLE();
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} else {
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ret = dispatch->handler(vcpu);
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}
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}
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}
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}
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return ret;
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return ret;
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@ -268,6 +260,7 @@ int32_t cr_access_vmexit_handler(struct acrn_vcpu *vcpu)
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uint64_t reg;
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uint64_t reg;
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uint32_t idx;
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uint32_t idx;
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uint64_t exit_qual;
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uint64_t exit_qual;
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int32_t ret = 0;
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exit_qual = vcpu->arch.exit_qualification;
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exit_qual = vcpu->arch.exit_qualification;
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idx = (uint32_t)vm_exit_cr_access_reg_idx(exit_qual);
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idx = (uint32_t)vm_exit_cr_access_reg_idx(exit_qual);
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@ -305,13 +298,14 @@ int32_t cr_access_vmexit_handler(struct acrn_vcpu *vcpu)
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break;
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break;
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default:
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default:
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panic("Unhandled CR access");
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panic("Unhandled CR access");
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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}
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TRACE_2L(TRACE_VMEXIT_CR_ACCESS, vm_exit_cr_access_type(exit_qual),
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TRACE_2L(TRACE_VMEXIT_CR_ACCESS, vm_exit_cr_access_type(exit_qual),
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vm_exit_cr_access_cr_num(exit_qual));
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vm_exit_cr_access_cr_num(exit_qual));
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return 0;
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return ret;
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}
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}
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/*
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/*
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@ -322,44 +316,43 @@ static int32_t xsetbv_vmexit_handler(struct acrn_vcpu *vcpu)
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{
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{
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int32_t idx;
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int32_t idx;
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uint64_t val64;
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uint64_t val64;
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int32_t ret = 0;
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val64 = exec_vmread(VMX_GUEST_CR4);
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val64 = exec_vmread(VMX_GUEST_CR4);
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if ((val64 & CR4_OSXSAVE) == 0UL) {
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if ((val64 & CR4_OSXSAVE) == 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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} else {
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idx = vcpu->arch.cur_context;
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if (idx >= NR_WORLD) {
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ret = -1;
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} else {
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/* to access XCR0,'rcx' should be 0 */
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if (vcpu_get_gpreg(vcpu, CPU_REG_RCX) != 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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} else {
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val64 = (vcpu_get_gpreg(vcpu, CPU_REG_RAX) & 0xffffffffUL) |
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(vcpu_get_gpreg(vcpu, CPU_REG_RDX) << 32U);
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/* bit 0(x87 state) of XCR0 can't be cleared */
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if ((val64 & 0x01UL) == 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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} else {
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/*
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* XCR0[2:1] (SSE state & AVX state) can't not be
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* set to 10b as it is necessary to set both bits
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* to use AVX instructions.
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*/
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if (((val64 >> 1U) & 0x3UL) == 0x2UL) {
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vcpu_inject_gp(vcpu, 0U);
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} else {
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write_xcr(0, val64);
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}
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}
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}
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}
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}
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}
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idx = vcpu->arch.cur_context;
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return ret;
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if (idx >= NR_WORLD) {
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return -1;
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}
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/*to access XCR0,'rcx' should be 0*/
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if (vcpu_get_gpreg(vcpu, CPU_REG_RCX) != 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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val64 = (vcpu_get_gpreg(vcpu, CPU_REG_RAX) & 0xffffffffUL) |
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(vcpu_get_gpreg(vcpu, CPU_REG_RDX) << 32U);
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/*bit 0(x87 state) of XCR0 can't be cleared*/
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if ((val64 & 0x01UL) == 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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/*XCR0[2:1] (SSE state & AVX state) can't not be
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*set to 10b as it is necessary to set both bits
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*to use AVX instructions.
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**/
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if (((val64 >> 1U) & 0x3UL) == 0x2UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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write_xcr(0, val64);
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return 0;
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}
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}
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static int32_t wbinvd_vmexit_handler(struct acrn_vcpu *vcpu)
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static int32_t wbinvd_vmexit_handler(struct acrn_vcpu *vcpu)
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