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acrn-config: add .clos to vm_configurations.c
1.Create board files for ehl-crb-b 2.Add .clos to vm_configurations.c Tracked-On: #5229 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
Wei Liu
wenlingz
parent
29ac258134
commit
52bb9d6983
199
misc/vm_configs/boards/ehl-crb-b/board.c
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199
misc/vm_configs/boards/ehl-crb-b/board.c
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@ -0,0 +1,199 @@
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: Intel Corporation
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* Version: EHLSFWI1.R00.2224.A00.2005281500
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* Release Date: 05/28/2020
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*
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* Base Board Information
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* Manufacturer: Intel Corporation
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* Product Name: ElkhartLake LPDDR4x T3 CRB
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* Version: 2
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*/
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#include <board.h>
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#include <vtd.h>
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#include <msr.h>
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#include <pci.h>
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#include <misc_cfg.h>
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static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
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{
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.type = DRHD0_DEVSCOPE0_TYPE,
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.id = DRHD0_DEVSCOPE0_ID,
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.bus = DRHD0_DEVSCOPE0_BUS,
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.devfun = DRHD0_DEVSCOPE0_PATH,
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},
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};
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static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
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{
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.type = DRHD1_DEVSCOPE0_TYPE,
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.id = DRHD1_DEVSCOPE0_ID,
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.bus = DRHD1_DEVSCOPE0_BUS,
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.devfun = DRHD1_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD1_DEVSCOPE1_TYPE,
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.id = DRHD1_DEVSCOPE1_ID,
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.bus = DRHD1_DEVSCOPE1_BUS,
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.devfun = DRHD1_DEVSCOPE1_PATH,
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},
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};
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static struct dmar_dev_scope drhd2_dev_scope[DRHD2_DEV_CNT] = {
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{
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.type = DRHD2_DEVSCOPE0_TYPE,
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.id = DRHD2_DEVSCOPE0_ID,
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.bus = DRHD2_DEVSCOPE0_BUS,
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.devfun = DRHD2_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD2_DEVSCOPE1_TYPE,
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.id = DRHD2_DEVSCOPE1_ID,
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.bus = DRHD2_DEVSCOPE1_BUS,
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.devfun = DRHD2_DEVSCOPE1_PATH,
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},
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{
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.type = DRHD2_DEVSCOPE2_TYPE,
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.id = DRHD2_DEVSCOPE2_ID,
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.bus = DRHD2_DEVSCOPE2_BUS,
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.devfun = DRHD2_DEVSCOPE2_PATH,
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},
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};
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static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
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{
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.dev_cnt = DRHD0_DEV_CNT,
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.segment = DRHD0_SEGMENT,
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.flags = DRHD0_FLAGS,
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.reg_base_addr = DRHD0_REG_BASE,
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.ignore = DRHD0_IGNORE,
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.devices = drhd0_dev_scope
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},
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{
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.dev_cnt = DRHD1_DEV_CNT,
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.segment = DRHD1_SEGMENT,
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.flags = DRHD1_FLAGS,
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.reg_base_addr = DRHD1_REG_BASE,
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.ignore = DRHD1_IGNORE,
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.devices = drhd1_dev_scope
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},
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{
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.dev_cnt = DRHD2_DEV_CNT,
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.segment = DRHD2_SEGMENT,
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.flags = DRHD2_FLAGS,
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.reg_base_addr = DRHD2_REG_BASE,
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.ignore = DRHD2_IGNORE,
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.devices = drhd2_dev_scope
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},
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};
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struct dmar_info plat_dmar_info = {
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.drhd_count = DRHD_COUNT,
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.drhd_units = drhd_info_array,
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};
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#ifdef CONFIG_RDT_ENABLED
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struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES] = {
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{
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.value.clos_mask = CLOS_MASK_0,
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.msr_index = MSR_IA32_L2_MASK_BASE + 0,
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},
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{
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.value.clos_mask = CLOS_MASK_1,
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.msr_index = MSR_IA32_L2_MASK_BASE + 1,
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},
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{
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.value.clos_mask = CLOS_MASK_2,
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.msr_index = MSR_IA32_L2_MASK_BASE + 2,
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},
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{
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.value.clos_mask = CLOS_MASK_3,
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.msr_index = MSR_IA32_L2_MASK_BASE + 3,
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},
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{
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.value.clos_mask = CLOS_MASK_4,
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.msr_index = MSR_IA32_L2_MASK_BASE + 4,
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},
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{
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.value.clos_mask = CLOS_MASK_5,
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.msr_index = MSR_IA32_L2_MASK_BASE + 5,
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},
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{
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.value.clos_mask = CLOS_MASK_6,
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.msr_index = MSR_IA32_L2_MASK_BASE + 6,
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},
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{
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.value.clos_mask = CLOS_MASK_7,
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.msr_index = MSR_IA32_L2_MASK_BASE + 7,
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},
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{
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.value.clos_mask = CLOS_MASK_8,
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.msr_index = MSR_IA32_L2_MASK_BASE + 8,
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},
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{
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.value.clos_mask = CLOS_MASK_9,
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.msr_index = MSR_IA32_L2_MASK_BASE + 9,
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},
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{
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.value.clos_mask = CLOS_MASK_10,
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.msr_index = MSR_IA32_L2_MASK_BASE + 10,
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},
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{
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.value.clos_mask = CLOS_MASK_11,
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.msr_index = MSR_IA32_L2_MASK_BASE + 11,
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},
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{
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.value.clos_mask = CLOS_MASK_12,
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.msr_index = MSR_IA32_L2_MASK_BASE + 12,
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},
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{
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.value.clos_mask = CLOS_MASK_13,
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.msr_index = MSR_IA32_L2_MASK_BASE + 13,
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},
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{
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.value.clos_mask = CLOS_MASK_14,
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.msr_index = MSR_IA32_L2_MASK_BASE + 14,
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},
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{
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.value.clos_mask = CLOS_MASK_15,
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.msr_index = MSR_IA32_L2_MASK_BASE + 15,
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},
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};
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struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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static const struct cpu_cx_data board_cpu_cx[3] = {
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{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0xFDU, 0x00U}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x418U, 0x00U}, /* C3 */
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};
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static const struct cpu_px_data board_cpu_px[2] = {
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{0x5DDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P0 */
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{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P1 */
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};
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const struct cpu_state_table board_cpu_state_tbl = {
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"Genuine Intel(R) CPU 0000 @ 1.50GHz",
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{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
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(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
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};
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const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
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#define VMSIX_ON_MSI_DEV0 .bdf.bits = {.b = 0x00U, .d = 0x1eU, .f =0x4U},
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#define VMSIX_ON_MSI_DEV1 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x1U},
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#define VMSIX_ON_MSI_DEV2 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x2U},
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const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM] = {
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{VMSIX_ON_MSI_DEV0},
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{VMSIX_ON_MSI_DEV1},
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{VMSIX_ON_MSI_DEV2},
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};
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23
misc/vm_configs/boards/ehl-crb-b/board_info.h
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23
misc/vm_configs/boards/ehl-crb-b/board_info.h
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_INFO_H
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#define BOARD_INFO_H
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#define MAX_PCPU_NUM 4U
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#define MAX_VMSIX_ON_MSI_PDEVS_NUM 3U
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#define MAX_HIDDEN_PDEVS_NUM 0U
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#define HI_MMIO_START ~0UL
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#define HI_MMIO_END 0UL
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#define HI_MMIO_SIZE 0x10000000UL
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#define P2SB_BAR_ADDR 0xFD000000UL
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#define BASE_GPIO_PORT_ID 0x69U
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#define MAX_GPIO_COMMUNITIES 0x6U
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#endif /* BOARD_INFO_H */
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88
misc/vm_configs/boards/ehl-crb-b/pci_devices.h
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88
misc/vm_configs/boards/ehl-crb-b/pci_devices.h
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: Intel Corporation
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* Version: EHLSFWI1.R00.2224.A00.2005281500
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* Release Date: 05/28/2020
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*
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* Base Board Information
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* Manufacturer: Intel Corporation
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* Product Name: ElkhartLake LPDDR4x T3 CRB
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* Version: 2
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*/
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#ifndef PCI_DEVICES_H_
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#define PCI_DEVICES_H_
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#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
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#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}
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#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U}
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#define SYSTEM_PERIPHERAL_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x01U}
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#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x02U}
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#define SERIAL_BUS_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x03U}
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#define SERIAL_BUS_CONTROLLER_6 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_7 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_8 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x01U}
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#define SERIAL_BUS_CONTROLLER_9 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x06U}
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#define SERIAL_BUS_CONTROLLER_10 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
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#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
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#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
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#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U}
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#define COMMUNICATION_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}
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#define COMMUNICATION_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U}
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
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#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}
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#define SD_HOST_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x01U}
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#define NON_VGA_UNCLASSIFIED_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x03U}
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#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U}
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#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x02U}
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#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x04U}
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#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
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#define MULTIMEDIA_AUDIO_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}
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#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}
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#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
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#endif /* PCI_DEVICES_H_ */
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85
misc/vm_configs/boards/ehl-crb-b/platform_acpi_info.h
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85
misc/vm_configs/boards/ehl-crb-b/platform_acpi_info.h
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING!
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*/
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#ifndef PLATFORM_ACPI_INFO_H
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#define PLATFORM_ACPI_INFO_H
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/*
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* BIOS Information
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* Vendor: Intel Corporation
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* Version: EHLSFWI1.R00.2224.A00.2005281500
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* Release Date: 05/28/2020
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*
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* Base Board Information
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* Manufacturer: Intel Corporation
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* Product Name: ElkhartLake LPDDR4x T3 CRB
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* Version: 2
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*/
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/* pm sstate data */
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#define PM1A_EVT_ADDRESS 0x1800UL
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#define PM1A_EVT_ACCESS_SIZE 0x2U
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#define PM1A_CNT_ADDRESS 0x1804UL
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#define WAKE_VECTOR_32 0x66BB000CUL
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#define WAKE_VECTOR_64 0x66BB0018UL
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#define RESET_REGISTER_ADDRESS 0xCF9UL
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#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
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#define RESET_REGISTER_VALUE 0x6U
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/* DRHD of DMAR */
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#define DRHD_COUNT 3U
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#define DRHD0_DEV_CNT 0x1U
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#define DRHD0_SEGMENT 0x0U
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#define DRHD0_FLAGS 0x0U
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#define DRHD0_REG_BASE 0xFED90000UL
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#define DRHD0_IGNORE true
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#define DRHD0_DEVSCOPE0_TYPE 0x1U
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#define DRHD0_DEVSCOPE0_ID 0x0U
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#define DRHD0_DEVSCOPE0_BUS 0x0U
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#define DRHD0_DEVSCOPE0_PATH 0x10U
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#define DRHD1_DEV_CNT 0x2U
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#define DRHD1_SEGMENT 0x0U
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#define DRHD1_FLAGS 0x1U
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#define DRHD1_REG_BASE 0xFED91000UL
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#define DRHD1_IGNORE false
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#define DRHD1_DEVSCOPE0_TYPE 0x3U
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#define DRHD1_DEVSCOPE0_ID 0x2U
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#define DRHD1_DEVSCOPE0_BUS 0x0U
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#define DRHD1_DEVSCOPE0_PATH 0xf7U
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#define DRHD1_DEVSCOPE1_TYPE 0x4U
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#define DRHD1_DEVSCOPE1_ID 0x0U
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#define DRHD1_DEVSCOPE1_BUS 0x0U
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#define DRHD1_DEVSCOPE1_PATH 0xf6U
|
||||
|
||||
#define DRHD2_DEV_CNT 0x3U
|
||||
#define DRHD2_SEGMENT 0x0U
|
||||
#define DRHD2_FLAGS 0x0U
|
||||
#define DRHD2_REG_BASE 0x00UL
|
||||
#define DRHD2_IGNORE false
|
||||
#define DRHD2_DEVSCOPE0_TYPE 0x5U
|
||||
#define DRHD2_DEVSCOPE0_ID 0x3U
|
||||
#define DRHD2_DEVSCOPE0_BUS 0x0U
|
||||
#define DRHD2_DEVSCOPE0_PATH 0xebU
|
||||
#define DRHD2_DEVSCOPE1_TYPE 0x5U
|
||||
#define DRHD2_DEVSCOPE1_ID 0x4U
|
||||
#define DRHD2_DEVSCOPE1_BUS 0x0U
|
||||
#define DRHD2_DEVSCOPE1_PATH 0xecU
|
||||
#define DRHD2_DEVSCOPE2_TYPE 0x5U
|
||||
#define DRHD2_DEVSCOPE2_ID 0x5U
|
||||
#define DRHD2_DEVSCOPE2_BUS 0x0U
|
||||
#define DRHD2_DEVSCOPE2_PATH 0xedU
|
||||
|
||||
/* PCI mmcfg base of MCFG */
|
||||
#define DEFAULT_PCI_MMCFG_BASE 0xc0000000UL
|
||||
|
||||
#endif /* PLATFORM_ACPI_INFO_H */
|
||||
@ -0,0 +1,37 @@
|
||||
# Board defconfig generated by acrn-config tool
|
||||
|
||||
CONFIG_BOARD="ehl-crb-b"
|
||||
CONFIG_HV_RAM_START=0x11000000
|
||||
CONFIG_HV_RAM_SIZE=0x14800000
|
||||
CONFIG_PLATFORM_RAM_SIZE=0x400000000
|
||||
CONFIG_LOW_RAM_SIZE=0x00010000
|
||||
CONFIG_SOS_RAM_SIZE=0x400000000
|
||||
CONFIG_UOS_RAM_SIZE=0x200000000
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_GPU_SBDF=0x00000010
|
||||
CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
|
||||
CONFIG_SCHED_BVT=y
|
||||
CONFIG_RELOC=y
|
||||
CONFIG_MULTIBOOT2=y
|
||||
CONFIG_RDT_ENABLED=y
|
||||
CONFIG_CDP_ENABLED=n
|
||||
CONFIG_HYPERV_ENABLED=y
|
||||
CONFIG_IOMMU_ENFORCE_SNP=n
|
||||
CONFIG_ACPI_PARSE_ENABLED=y
|
||||
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
|
||||
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
|
||||
CONFIG_IOMMU_BUS_NUM=0x100
|
||||
CONFIG_MAX_IOAPIC_NUM=1
|
||||
CONFIG_MAX_IR_ENTRIES=256
|
||||
CONFIG_MAX_PCI_DEV_NUM=96
|
||||
CONFIG_MAX_IOAPIC_LINES=120
|
||||
CONFIG_MAX_PT_IRQ_ENTRIES=256
|
||||
CONFIG_MAX_MSIX_TABLE_NUM=64
|
||||
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
|
||||
CONFIG_SERIAL_PCI=y
|
||||
CONFIG_SERIAL_PCI_BDF="00:19.2"
|
||||
CONFIG_LOG_BUF_SIZE=0x40000
|
||||
CONFIG_NPK_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_MEM_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_LOG_DESTINATION=7
|
||||
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3
|
||||
58
misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h
Normal file
58
misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MISC_CFG_H
|
||||
#define MISC_CFG_H
|
||||
|
||||
#define SOS_ROOTFS "root=/dev/mmcblk0p2 "
|
||||
#define SOS_CONSOLE "console=ttyS0 "
|
||||
#define SOS_COM1_BASE 0x3F8U
|
||||
#define SOS_COM1_IRQ 3U
|
||||
#define SOS_COM2_BASE 0x2E8U
|
||||
#define SOS_COM2_IRQ 4U
|
||||
|
||||
#define SOS_BOOTARGS_DIFF "rw " \
|
||||
"rootwait " \
|
||||
"console=tty0 " \
|
||||
"consoleblank=0 " \
|
||||
"no_timer_check " \
|
||||
"quiet " \
|
||||
"loglevel=3 " \
|
||||
"i915.nuclear_pageflip=1"
|
||||
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
#define HV_SUPPORTED_MAX_CLOS 16U
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 16U
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 16U
|
||||
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
|
||||
#define VM0_VCPU_CLOS {0U}
|
||||
#define VM1_VCPU_CLOS {0U, 0U}
|
||||
#define VM2_VCPU_CLOS {0U, 0U}
|
||||
#define VM3_VCPU_CLOS {0U, 0U}
|
||||
#define VM4_VCPU_CLOS {0U, 0U}
|
||||
#define VM5_VCPU_CLOS {0U, 0U}
|
||||
#define VM6_VCPU_CLOS {0U, 0U}
|
||||
#define VM7_VCPU_CLOS {0U, 0U}
|
||||
#endif
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
12
misc/vm_configs/scenarios/industry/ehl-crb-b/pci_dev.c
Normal file
12
misc/vm_configs/scenarios/industry/ehl-crb-b/pci_dev.c
Normal file
@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
10
misc/vm_configs/scenarios/industry/ehl-crb-b/vbar_base.h
Normal file
10
misc/vm_configs/scenarios/industry/ehl-crb-b/vbar_base.h
Normal file
@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
@ -14,6 +14,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
|
||||
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM0_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
|
||||
.memory = {
|
||||
.start_hpa = 0UL,
|
||||
@ -40,6 +43,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM1 */
|
||||
CONFIG_POST_STD_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM1_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -53,6 +59,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM2 */
|
||||
CONFIG_POST_RT_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM2_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -69,6 +78,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM3 */
|
||||
CONFIG_POST_STD_VM(2),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM3_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -82,6 +94,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM4 */
|
||||
CONFIG_POST_STD_VM(3),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM4_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM4_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -95,6 +110,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM5 */
|
||||
CONFIG_POST_STD_VM(4),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM5_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM5_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -108,6 +126,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM6 */
|
||||
CONFIG_POST_STD_VM(5),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM6_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM6_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
@ -121,6 +142,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
},
|
||||
{ /* VM7 */
|
||||
CONFIG_KATA_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM7_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM7_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user