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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-04-29 20:24:00 +00:00
hv:Add vpin to ptdev entry mapping for vpic/vioapic
Now if the vmexit reason is virtulized EOI for level triggered interrupts, HV will loop all the ptdev entries, it is time-consuming, this patch add vpin to ptdev entry mapping for vpic and vioapic when add intx entry for a vm,it can use the ptdev entry directly according to the mapping for vpin and ptdev entry when EOI vmexit. v3-->v4: -- add check vpin in remove_intx_remapping -- move check vpin from ptdev_add_intx_remapping to add_intx_remapping Tracked-On: #861 Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Reviewed-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
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@ -39,6 +39,19 @@ ptdev_lookup_entry_by_sid(uint32_t intr_type,
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return NULL;
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}
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static inline struct ptdev_remapping_info *
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ptdev_lookup_entry_by_vpin(struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin)
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{
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struct ptdev_remapping_info *entry;
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if (pic_pin) {
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entry = vm->arch_vm.vpic.vpin_to_pt_entry[virt_pin];
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} else {
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entry = vm->arch_vm.vioapic.vpin_to_pt_entry[virt_pin];
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}
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return entry;
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}
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#ifdef HV_DEBUG
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static bool ptdev_hv_owned_intx(const struct acrn_vm *vm, const union source_id *virt_sid)
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{
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@ -277,6 +290,12 @@ static struct ptdev_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint8
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DEFINE_IOAPIC_SID(virt_sid, virt_pin, vpin_src);
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uint32_t phys_irq = pin_to_irq(phys_pin);
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if ((!pic_pin && virt_pin >= vioapic_pincount(vm))
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|| (pic_pin && virt_pin >= vpic_pincount())) {
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pr_err("ptdev_add_intx_remapping fails!\n");
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return NULL;
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}
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if (!irq_is_gsi(phys_irq)) {
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pr_err("%s, invalid phys_pin: %d <-> irq: 0x%x is not a GSI\n", __func__, phys_pin, phys_irq);
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return NULL;
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@ -284,7 +303,7 @@ static struct ptdev_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint8
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entry = ptdev_lookup_entry_by_sid(PTDEV_INTR_INTX, &phys_sid, NULL);
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if (entry == NULL) {
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if (ptdev_lookup_entry_by_sid(PTDEV_INTR_INTX, &virt_sid, vm) != NULL) {
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if (ptdev_lookup_entry_by_vpin(vm, virt_pin, pic_pin) != NULL) {
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pr_err("INTX re-add vpin %d", virt_pin);
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return NULL;
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}
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@ -314,26 +333,33 @@ static struct ptdev_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint8
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* required. */
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}
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dev_dbg(ACRN_DBG_IRQ, "VM%d INTX add pin mapping vpin%d:ppin%d", vm->vm_id, virt_pin, phys_pin);
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if (pic_pin) {
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vm->arch_vm.vpic.vpin_to_pt_entry[virt_pin] = entry;
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} else {
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vm->arch_vm.vioapic.vpin_to_pt_entry[virt_pin] = entry;
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}
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dev_dbg(ACRN_DBG_IRQ, "VM%d INTX add pin mapping vpin%d:ppin%d", entry->vm->vm_id, virt_pin, phys_pin);
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return entry;
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}
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/* deactive & remove mapping entry of vpin for vm */
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static void remove_intx_remapping(const struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin)
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static void remove_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin)
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{
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uint32_t phys_irq;
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struct ptdev_remapping_info *entry;
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enum ptdev_vpin_source vpin_src =
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pic_pin ? PTDEV_VPIN_PIC : PTDEV_VPIN_IOAPIC;
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DEFINE_IOAPIC_SID(virt_sid, virt_pin, vpin_src);
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entry = ptdev_lookup_entry_by_sid(PTDEV_INTR_INTX, &virt_sid, vm);
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if (entry == NULL) {
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if ((!pic_pin && virt_pin >= vioapic_pincount(vm))
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|| (pic_pin && virt_pin >= vpic_pincount())) {
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pr_err("virtual irq pin is invalid!\n");
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return;
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}
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entry = ptdev_lookup_entry_by_vpin(vm, virt_pin, pic_pin);
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if (entry == NULL) {
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return;
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}
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if (is_entry_active(entry)) {
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phys_irq = entry->allocated_pirq;
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/* disable interrupt */
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@ -342,13 +368,18 @@ static void remove_intx_remapping(const struct acrn_vm *vm, uint8_t virt_pin, bo
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ptdev_deactivate_entry(entry);
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dev_dbg(ACRN_DBG_IRQ,
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"deactive %s intx entry:ppin=%d, pirq=%d ",
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vpin_src == PTDEV_VPIN_PIC ?
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"vPIC" : "vIOAPIC",
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pic_pin ? "vPIC" : "vIOAPIC",
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entry->phys_sid.intx_id.pin, phys_irq);
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dev_dbg(ACRN_DBG_IRQ, "from vm%d vpin=%d\n",
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entry->vm->vm_id, virt_pin);
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}
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if (pic_pin) {
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vm->arch_vm.vpic.vpin_to_pt_entry[virt_pin] = NULL;
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} else {
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vm->arch_vm.vioapic.vpin_to_pt_entry[virt_pin] = NULL;
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}
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release_entry(entry);
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}
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@ -464,9 +495,9 @@ void ptdev_intx_ack(struct acrn_vm *vm, uint8_t virt_pin,
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{
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uint32_t phys_irq;
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struct ptdev_remapping_info *entry;
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DEFINE_IOAPIC_SID(virt_sid, virt_pin, vpin_src);
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bool pic_pin = (vpin_src == PTDEV_VPIN_PIC);
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entry = ptdev_lookup_entry_by_sid(PTDEV_INTR_INTX, &virt_sid, vm);
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entry = ptdev_lookup_entry_by_vpin(vm, virt_pin, pic_pin);
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if (entry == NULL) {
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return;
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}
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@ -600,6 +631,7 @@ int ptdev_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin,
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struct ptdev_remapping_info *entry;
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bool need_switch_vpin_src = false;
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DEFINE_IOAPIC_SID(virt_sid, virt_pin, vpin_src);
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bool pic_pin = (vpin_src == PTDEV_VPIN_PIC);
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/*
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* virt pin could come from vpic master, vpic slave or vioapic
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@ -620,10 +652,9 @@ int ptdev_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin,
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#endif
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/* query if we have virt to phys mapping */
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spinlock_obtain(&ptdev_lock);
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entry = ptdev_lookup_entry_by_sid(PTDEV_INTR_INTX, &virt_sid, vm);
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entry = ptdev_lookup_entry_by_vpin(vm, virt_pin, pic_pin);
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if (entry == NULL) {
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if (is_vm0(vm)) {
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bool pic_pin = (vpin_src == PTDEV_VPIN_PIC);
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/* for vm0, there is chance of vpin source switch
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* between vPIC & vIOAPIC for one legacy phys_pin.
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@ -633,12 +664,9 @@ int ptdev_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin,
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* switch vpin source is needed
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*/
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if (virt_pin < NR_LEGACY_PIN) {
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DEFINE_IOAPIC_SID(tmp_vsid,
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pic_ioapic_pin_map[virt_pin],
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pic_pin ? PTDEV_VPIN_IOAPIC :
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PTDEV_VPIN_PIC);
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entry = ptdev_lookup_entry_by_sid(
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PTDEV_INTR_INTX, &tmp_vsid, vm);
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uint8_t vpin = pic_ioapic_pin_map[virt_pin];
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entry = ptdev_lookup_entry_by_vpin(vm, vpin, !pic_pin);
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if (entry != NULL) {
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need_switch_vpin_src = true;
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}
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@ -707,12 +735,6 @@ int ptdev_add_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, uint8_t phys_
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{
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struct ptdev_remapping_info *entry;
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if ((!pic_pin && virt_pin >= vioapic_pincount(vm))
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|| (pic_pin && virt_pin >= vpic_pincount())) {
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pr_err("ptdev_add_intx_remapping fails!\n");
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return -EINVAL;
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}
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spinlock_obtain(&ptdev_lock);
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entry = add_intx_remapping(vm, virt_pin, phys_pin, pic_pin);
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spinlock_release(&ptdev_lock);
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@ -723,7 +745,7 @@ int ptdev_add_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, uint8_t phys_
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/*
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* @pre vm != NULL
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*/
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void ptdev_remove_intx_remapping(const struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin)
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void ptdev_remove_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin)
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{
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spinlock_obtain(&ptdev_lock);
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remove_intx_remapping(vm, virt_pin, pic_pin);
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@ -31,10 +31,6 @@
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#define ACRN_DBG_PIC 6U
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#define NR_VPIC_PINS_PER_CHIP 8U
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#define NR_VPIC_PINS_TOTAL 16U
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#define VPIC_INVALID_PIN 0xffU
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static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, uint8_t level);
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static inline bool master_pic(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259)
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@ -119,7 +119,7 @@ int ptdev_add_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, uint8_t phys_
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* @pre vm != NULL
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*
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*/
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void ptdev_remove_intx_remapping(const struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin);
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void ptdev_remove_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, bool pic_pin);
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/**
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* @brief Add interrupt remapping entry/entries for MSI/MSI-x as pre-hold mapping.
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@ -41,6 +41,7 @@
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#define VIOAPIC_BASE 0xFEC00000UL
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#define VIOAPIC_SIZE 4096UL
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#define VIOAPIC_MAX_PIN 256U
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#define REDIR_ENTRIES_HW 120U /* SOS align with native ioapic */
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#define STATE_BITMAP_SIZE INT_DIV_ROUNDUP(REDIR_ENTRIES_HW, 64U)
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@ -53,6 +54,7 @@ struct acrn_vioapic {
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union ioapic_rte rtbl[REDIR_ENTRIES_HW];
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/* pin_state status bitmap: 1 - high, 0 - low */
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uint64_t pin_state[STATE_BITMAP_SIZE];
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struct ptdev_remapping_info *vpin_to_pt_entry[VIOAPIC_MAX_PIN];
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};
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void vioapic_init(struct acrn_vm *vm);
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@ -92,6 +92,10 @@
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#define IO_ELCR1 0x4d0U
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#define IO_ELCR2 0x4d1U
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#define NR_VPIC_PINS_PER_CHIP 8U
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#define NR_VPIC_PINS_TOTAL 16U
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#define VPIC_INVALID_PIN 0xffU
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enum vpic_trigger {
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EDGE_TRIGGER,
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LEVEL_TRIGGER
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@ -124,6 +128,7 @@ struct acrn_vpic {
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struct acrn_vm *vm;
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spinlock_t lock;
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struct i8259_reg_state i8259[2];
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struct ptdev_remapping_info *vpin_to_pt_entry[NR_VPIC_PINS_TOTAL];
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};
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void vpic_init(struct acrn_vm *vm);
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