diff --git a/devicemodel/core/sw_load_common.c b/devicemodel/core/sw_load_common.c
index ad1c1fc91..1f7588a54 100644
--- a/devicemodel/core/sw_load_common.c
+++ b/devicemodel/core/sw_load_common.c
@@ -268,6 +268,9 @@ acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
 			removed++;
 		}
 	} else {
+		/* Fix-Me: e820[LOWRAM_E820_ENTRY+2] can be used as RAM 
+			only when ctx->lowmem is higher than PSRAM area.
+			also, the length should be adjusted to ctx->lowmem-baseaddr */
 		e820[LOWRAM_E820_ENTRY+2].type = E820_TYPE_RAM;
 	}
 
diff --git a/devicemodel/include/ptct.h b/devicemodel/include/ptct.h
new file mode 100644
index 000000000..0a9f830ec
--- /dev/null
+++ b/devicemodel/include/ptct.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PTCT_H
+#define PTCT_H
+
+#define PSRAM_BASE_HPA	0x40080000UL
+#define PSRAM_BASE_GPA	0x40080000UL
+#define PSRAM_MAX_SIZE	0x00800000UL
+
+#endif  /* PTCT_H */