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fix "negative shift"

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MISRA C doesn't allowed negative shift, changed any potential signed value
to unsigned value.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
2018-06-22 10:05:25 +08:00
committed by lijinxia
parent de31cf4f5f
commit 58672cb562
7 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/cpu.c
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@@ -59,7 +59,7 @@ int ibrs_type;
inline bool cpu_has_cap(uint32_t bit) inline bool cpu_has_cap(uint32_t bit)
{ {
int feat_idx = bit >> 5; int feat_idx = bit >> 5;
int feat_bit = bit & 0x1fU; uint32_t feat_bit = bit & 0x1fU;
if (feat_idx >= FEATURE_WORDS) if (feat_idx >= FEATURE_WORDS)
return false; return false;

3
hypervisor/arch/x86/guest/guest.c
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@@ -127,7 +127,8 @@ enum vm_paging_mode get_vcpu_paging_mode(struct vcpu *vcpu)
static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info, static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info,
uint64_t gva, uint64_t *gpa, uint32_t *err_code) uint64_t gva, uint64_t *gpa, uint32_t *err_code)
{ {
int i, index, shift; int i, index;
uint32_t shift;
uint8_t *base; uint8_t *base;
uint64_t entry; uint64_t entry;
uint64_t addr, page_size; uint64_t addr, page_size;

3
hypervisor/arch/x86/guest/instr_emul.c
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@@ -1407,7 +1407,8 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
void *memarg) void *memarg)
{ {
uint64_t val, rflags; uint64_t val, rflags;
int error, bitmask, bitoff; int error, bitmask;
uint32_t bitoff;
/* /*
* 0F BA is a Group 8 extended opcode. * 0F BA is a Group 8 extended opcode.

8
hypervisor/arch/x86/guest/vioapic.c
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@@ -223,8 +223,8 @@ vioapic_update_tmr(struct vcpu *vcpu)
static uint32_t static uint32_t
vioapic_read(struct vioapic *vioapic, uint32_t addr) vioapic_read(struct vioapic *vioapic, uint32_t addr)
{ {
uint32_t regnum; uint32_t regnum, rshift;
int pin, rshift; int pin;
regnum = addr & 0xffU; regnum = addr & 0xffU;
switch (regnum) { switch (regnum) {
@@ -291,8 +291,8 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
{ {
uint64_t data64, mask64; uint64_t data64, mask64;
uint64_t last, new, changed; uint64_t last, new, changed;
uint32_t regnum; uint32_t regnum, lshift;
int pin, lshift; int pin;
regnum = addr & 0xffUL; regnum = addr & 0xffUL;
switch (regnum) { switch (regnum) {

9
hypervisor/arch/x86/guest/vlapic.c
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@@ -712,8 +712,9 @@ vlapic_update_ppr(struct vlapic *vlapic)
/* update ppr */ /* update ppr */
{ {
int i, lastprio, curprio, vector, idx; int i, lastprio, curprio, idx;
struct lapic_reg *isrptr; struct lapic_reg *isrptr;
uint32_t vector;
if (vlapic->isrvec_stk_top == 0 && isrvec != 0) if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
panic("isrvec_stk is corrupted: %d", isrvec); panic("isrvec_stk is corrupted: %d", isrvec);
@@ -738,9 +739,9 @@ vlapic_update_ppr(struct vlapic *vlapic)
*/ */
i = 1; i = 1;
isrptr = &vlapic->apic_page->isr[0]; isrptr = &vlapic->apic_page->isr[0];
for (vector = 0; vector < 256; vector++) { for (vector = 0U; vector < 256U; vector++) {
idx = vector / 32; idx = vector / 32U;
if ((isrptr[idx].val & (1U << (vector % 32))) != 0U) { if ((isrptr[idx].val & (1U << (vector % 32U))) != 0U) {
if ((i > vlapic->isrvec_stk_top) || if ((i > vlapic->isrvec_stk_top) ||
((i < ISRVEC_STK_SIZE) && ((i < ISRVEC_STK_SIZE) &&
(vlapic->isrvec_stk[i] != vector))) { (vlapic->isrvec_stk[i] != vector))) {

2
hypervisor/arch/x86/ioapic.c
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@@ -191,7 +191,7 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
rte.lo_32 |= IOAPIC_RTE_INTALO; rte.lo_32 |= IOAPIC_RTE_INTALO;
/* Dest field */ /* Dest field */
rte.hi_32 |= ALL_CPUS_MASK << 24; rte.hi_32 |= ALL_CPUS_MASK << 24U;
return rte; return rte;
} }

2
hypervisor/include/arch/x86/vtd.h
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@@ -66,7 +66,7 @@
#define iommu_cap_plmr(c) (((c) >> 5) & 1UL) #define iommu_cap_plmr(c) (((c) >> 5) & 1UL)
#define iommu_cap_rwbf(c) (((c) >> 4) & 1UL) #define iommu_cap_rwbf(c) (((c) >> 4) & 1UL)
#define iommu_cap_afl(c) (((c) >> 3) & 1UL) #define iommu_cap_afl(c) (((c) >> 3) & 1UL)
#define iommu_cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7UL))) #define iommu_cap_ndoms(c) ((1U) << (4U + 2U * ((c) & 0x7U)))
/* /*
* Decoding Extended Capability Register * Decoding Extended Capability Register